Lines Matching +full:8 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
24 #define DEV_PORT_MISC_HDX_FAST_DIS BIT(0)
26 #define DEV_EEE_CFG_EEE_ENA BIT(22)
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
36 #define DEV_EEE_CFG_PORT_LPI BIT(0)
44 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
45 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
47 #define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
48 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
49 #define DEV_MAC_MODE_CFG_FDX_ENA BIT(0)
54 #define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2)
55 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA BIT(1)
56 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
58 #define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
60 #define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
61 #define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16)
62 #define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
63 #define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
64 #define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
71 #define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
72 #define DEV_MAC_HDX_CFG_OB_ENA BIT(25)
73 #define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24)
77 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
78 #define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
82 #define DEV_MAC_DBG_CFG_TBI_MODE BIT(4)
83 #define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0)
85 #define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9)
86 #define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8)
87 #define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7)
88 #define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6)
89 #define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5)
90 #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
91 #define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3)
92 #define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2)
93 #define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1)
94 #define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0)
96 #define DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA BIT(0)
97 #define DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA BIT(4)
98 #define DEV_MM_CONFIG_ENABLE_CONFIG_KEEP_S_AFTER_D BIT(8)
100 #define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS BIT(0)
108 #define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STATUS BIT(0)
109 #define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STICKY BIT(4)
110 #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE(x) (((x) << 8) & GENMASK(10, 8))
111 #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_M GENMASK(10, 8)
112 #define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(x) (((x) & GENMASK(10, 8)) >> 8)
113 #define DEV_MM_STAT_MM_STATUS_UNEXP_RX_PFRM_STICKY BIT(12)
114 #define DEV_MM_STAT_MM_STATUS_UNEXP_TX_PFRM_STICKY BIT(16)
115 #define DEV_MM_STAT_MM_STATUS_MM_RX_FRAME_STATUS BIT(20)
116 #define DEV_MM_STAT_MM_STATUS_MM_TX_FRAME_STATUS BIT(24)
117 #define DEV_MM_STAT_MM_STATUS_MM_TX_PRMPT_STATUS BIT(28)
119 #define PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
120 #define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
121 #define PCS1G_CFG_PCS_ENA BIT(0)
123 #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
124 #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
126 #define PCS1G_SD_CFG_SD_SEL BIT(8)
127 #define PCS1G_SD_CFG_SD_POL BIT(4)
128 #define PCS1G_SD_CFG_SD_ENA BIT(0)
133 #define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
134 #define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
135 #define PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
140 #define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0)
142 #define PCS1G_LB_CFG_RA_ENA BIT(4)
143 #define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
144 #define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
146 #define PCS1G_DBG_CFG_UDLT BIT(0)
148 #define PCS1G_CDET_CFG_CDET_ENA BIT(0)
153 #define PCS1G_ANEG_STATUS_PR BIT(4)
154 #define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
155 #define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
160 #define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
161 #define PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
162 #define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
164 #define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
165 #define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
167 #define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20)
168 #define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17)
169 #define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16)
173 #define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0)
175 #define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16)
176 #define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12)
177 #define PCS1G_LPI_STATUS_RX_QUIET BIT(9)
178 #define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8)
179 #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4)
180 #define PCS1G_LPI_STATUS_TX_QUIET BIT(1)
181 #define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0)
183 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))
184 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)
185 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)
186 #define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4)
187 #define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0)
189 #define DEV_PCS_FX100_CFG_SD_SEL BIT(26)
190 #define DEV_PCS_FX100_CFG_SD_POL BIT(25)
191 #define DEV_PCS_FX100_CFG_SD_ENA BIT(24)
192 #define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
193 #define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
200 #define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
204 #define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
205 #define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
206 #define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
207 #define DEV_PCS_FX100_CFG_PCS_ENA BIT(0)
209 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))
210 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)
211 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)
212 #define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
213 #define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
214 #define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
215 #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
216 #define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2)
217 #define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
218 #define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0)