Lines Matching +full:low +full:- +full:power +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define AT91_DDRSDRC_MR 0x00 /* Mode Register */
12 #define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
68 #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "F…
69 #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "…
73 #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
80 #define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */
84 #define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
88 #define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
89 #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
114 #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */