Lines Matching +full:5 +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
32 #define OPA_LINKDOWN_REASON_BAD_SLID 5
61 /* 34 -reserved */
64 /* 37-38 reserved */
68 /* 42-48 reserved */
84 /* 64-255 reserved */
87 /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
108 #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
146 /* Filter Raw In/Out bits 1 and 2 were removed */
164 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
181 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
186 /* 7 bits reserved */
195 /* 2 bits reserved */
225 OPA_PI_MASK_VL_STALL = (0x03 << 5),
242 u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */
244 u8 portphysstate_portstate; /* 4 bits, 4 bits */
259 u8 cap; /* 3 res, 5 bits */
267 u8 port_phys_conf; /* 4 res, 4 bits */
269 u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */
270 u8 smsl; /* 3 res, 5 bits */
273 u8 operational_vls; /* 3 res, 5 bits */
280 __be32 sm_trap_qp; /* 8 bits, 24 bits */
282 __be32 sa_qp; /* 8 bits, 24 bits */
286 u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */
304 __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */
305 __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */
313 __be16 interleave; /* 2 res, 2,2,5,5 */
332 __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */
342 u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */
346 u8 vlstall_hoqlife; /* 3 bits, 5 bits */
377 u8 mtucap; /* 4 res, 4 bits */
379 u8 resptimevalue; /* 3 res, 5 bits */