Lines Matching +full:serial +full:- +full:id
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 #define RIO_ASM_ID_MASK 0xffff0000 /* [I] Asm ID Mask */
60 #define RIO_SRC_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
69 #define RIO_SRC_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
74 #define RIO_DST_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
83 #define RIO_DST_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
87 #define RIO_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
96 #define RIO_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
98 /* 0x20-0x30 *//* Reserved */
100 #define RIO_SWITCH_RT_LIMIT 0x34 /* [III, 1.3] Switch Route Table Destination ID Limit CAR */
147 #define RIO_PELL_ADDR_66 0x00000004 /* [I] 66-bit addr */
148 #define RIO_PELL_ADDR_50 0x00000002 /* [I] 50-bit addr */
149 #define RIO_PELL_ADDR_34 0x00000001 /* [I] 34-bit addr */
151 /* 0x50-0x54 *//* Reserved */
156 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
160 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
168 /* 0x7c-0xf8 *//* Reserved */
169 /* 0x100-0xfff8 *//* [I] Extended Features Space */
170 /* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */
183 * EFB ID. Extended feature block offsets in the definitions are
195 #define RIO_EFB_SER_EP_M1_ID 0x0001 /* [VI] LP-Serial EP Devices, Map I */
196 #define RIO_EFB_SER_EP_SW_M1_ID 0x0002 /* [VI] LP-Serial EP w SW Recovery Devices, Map I */
197 #define RIO_EFB_SER_EPF_M1_ID 0x0003 /* [VI] LP-Serial EP Free Devices, Map I */
198 #define RIO_EFB_SER_EP_ID 0x0004 /* [VI] LP-Serial EP Devices, RIO 1.2 */
199 #define RIO_EFB_SER_EP_REC_ID 0x0005 /* [VI] LP-Serial EP w SW Recovery Devices, RIO 1.2 */
200 #define RIO_EFB_SER_EP_FREE_ID 0x0006 /* [VI] LP-Serial EP Free Devices, RIO 1.2 */
202 #define RIO_EFB_SER_EPF_SW_M1_ID 0x0009 /* [VI] LP-Serial EP Free w SW Recovery Devices, Map I */
204 #define RIO_EFB_SER_EP_M2_ID 0x0011 /* [VI] LP-Serial EP Devices, Map II */
205 #define RIO_EFB_SER_EP_SW_M2_ID 0x0012 /* [VI] LP-Serial EP w SW Recovery Devices, Map II */
206 #define RIO_EFB_SER_EPF_M2_ID 0x0013 /* [VI] LP-Serial EP Free Devices, Map II */
207 #define RIO_EFB_ERR_MGMNT_HS 0x0017 /* [VIII] Error Management Extensions, Hot-Swap only */
208 #define RIO_EFB_SER_EPF_SW_M2_ID 0x0019 /* [VI] LP-Serial EP Free w SW Recovery Devices, Map II */
211 * Physical LP-Serial Registers Definitions
213 * n - port number, m - Register Map Type (1 or 2)
225 #define RIO_MNT_REQ_CMD_RD 0x03 /* Reset-device command */
226 #define RIO_MNT_REQ_CMD_IS 0x04 /* Input-status command */
231 #define RIO_PORT_N_ACK_STS_CSR(n) (0x48 + (n) * 0x20) /* Only in RM-I */
239 #define RIO_PORT_N_ERR_STS_OUT_ES 0x00010000 /* Output Error-stopped */
240 #define RIO_PORT_N_ERR_STS_INP_ES 0x00000100 /* Input Error-stopped */
241 #define RIO_PORT_N_ERR_STS_PW_PEND 0x00000010 /* Port-Write Pending */
255 #define RIO_PORT_N_OB_ACK_CSR(n) (0x60 + (n) * 0x40) /* Only in RM-II */
259 #define RIO_PORT_N_IB_ACK_CSR(n) (0x64 + (n) * 0x40) /* Only in RM-II */
263 * Device-based helper macros for serial port register access.
264 * d - pointer to rapidio device object, n - port number
268 (d->phys_efptr + RIO_PORT_N_MNT_REQ_CSR(n, d->phys_rmap))
271 (d->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(n, d->phys_rmap))
274 (d->phys_efptr + RIO_PORT_N_ACK_STS_CSR(n))
277 (d->phys_efptr + RIO_PORT_N_CTL2_CSR(n, d->phys_rmap))
280 (d->phys_efptr + RIO_PORT_N_ERR_STS_CSR(n, d->phys_rmap))
283 (d->phys_efptr + RIO_PORT_N_CTL_CSR(n, d->phys_rmap))
286 (d->phys_efptr + RIO_PORT_N_OB_ACK_CSR(n))
289 (d->phys_efptr + RIO_PORT_N_IB_ACK_CSR(n))
294 * Extended Features Block ID=0x0007
309 #define RIO_EM_LTL_DEVID_CAP 0x018 /* Logical/Transport Layer Device ID Capture CSR */
312 #define RIO_EM_LTL_SID32_CAP 0x024 /* Logical/Transport Layer Dev32 source ID Capture CSR */
313 #define RIO_EM_PW_TGT_DEVID 0x028 /* Port-write Target deviceID CSR */
314 #define RIO_EM_PW_TGT_DEVID_D16M 0xff000000 /* Port-write Target DID16 MSB */
315 #define RIO_EM_PW_TGT_DEVID_D8 0x00ff0000 /* Port-write Target DID16 LSB or DID8 */
316 #define RIO_EM_PW_TGT_DEVID_DEV16 0x00008000 /* Port-write Target DID16 LSB or DID8 */
317 #define RIO_EM_PW_TGT_DEVID_DEV32 0x00004000 /* Port-write Target DID16 LSB or DID8 */
318 #define RIO_EM_PKT_TTL 0x02c /* Packet Time-to-live CSR */
319 #define RIO_EM_PKT_TTL_VAL 0xffff0000 /* Packet Time-to-live value */
320 #define RIO_EM_PW_TGT32_DEVID 0x030 /* Port-write Dev32 Target deviceID CSR */
321 #define RIO_EM_PW_TX_CTRL 0x034 /* Port-write Transmission Control CSR */
322 #define RIO_EM_PW_TX_CTRL_PW_DIS 0x00000001 /* Port-write Transmission Disable bit */
324 /* Per-Port EM Registers */
349 * Switch Routing Table Register Block ID=0x000E (RapidIO 3.0+, part 3)
374 /* Per-Port Routing Table registers.