Lines Matching +full:serial +full:- +full:out

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * This driver supports the following PXA CPU/SSP ports:-
29  * SSP Serial Port Registers
40 #define SSTO		(0x28)  /* SSP Time Out Register */
41 #define SSPSP		(0x2C)  /* SSP Programmable Serial Protocol */
50 #define SSCR0_DataSize(x)  ((x) - 1)	/* Data Size Select [4..16] */
52 #define SSCR0_Motorola	(0x0 << 4)	/* Motorola's Serial Peripheral Interface (SPI) */
53 #define SSCR0_TI	(0x1 << 4)	/* Texas Instruments' Synchronous Serial Protocol (SSP) */
56 #define SSCR0_SSE	BIT(7)		/* Synchronous Serial Port Enable */
57 #define SSCR0_SCR(x)	((x) << 8)	/* Serial Clock Rate (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)	/* Time slots per frame [1..8] */
72 #define SSCR1_LBM	BIT(2)		/* Loop-Back Mode */
92 #define SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..16] */
94 #define SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..16] */
103 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..4] */
105 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..4] */
112 #define QUARK_X1000_SSCR0_DataSize(x)	((x) - 1)	/* Data Size Select [4..32] */
114 #define QUARK_X1000_SSCR0_Motorola	(0x0 << 5)	/* Motorola's Serial Peripheral Interface (SPI) */
123 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..32] */
125 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11)	/* level [1..32] */
130 #define SSCR0_TISSP		(1 << 4)	/* TI Sync Serial Protocol */
131 #define SSCR0_PSP		(3 << 4)	/* PSP - Programmable Serial Protocol */
137 #define SSCR1_TINTE		BIT(19)		/* Receiver Time-out Interrupt enable */
143 #define SSCR1_SCLKDIR		BIT(25)		/* Serial Bit Rate Clock Direction */
152 #define SSSR_TINT		BIT(19)		/* Receiver Time-out Interrupt */
158 #define SSPSP_SCMODE(x)		((x) << 0)	/* Serial Bit Rate Clock Mode */
159 #define SSPSP_SFRMP		BIT(2)		/* Serial Frame Polarity */
163 #define SSPSP_SFRMDLY(x)	((x) << 9)	/* Serial Frame Delay */
164 #define SSPSP_SFRMWDTH(x)	((x) << 16)	/* Serial Frame Width */
197 #define SFIFOTT_TxThresh(x)	(((x) - 1) << 0)	/* TX FIFO trigger threshold / level */
199 #define SFIFOTT_RxThresh(x)	(((x) - 1) << 16)	/* RX FIFO trigger threshold / level */
203 #define SSITF_TxHiThresh(x)	(((x) - 1) << 0)
204 #define SSITF_TxLoThresh(x)	(((x) - 1) << 8)
207 #define SSIRF_RxThresh(x)	((x) - 1)
211 #define SSPSP2		(0x44)	/* SSP Programmable Serial Protocol 2 */
253  * pxa_ssp_write_reg - Write to a SSP register
261 	__raw_writel(val, dev->mmio_base + reg);  in pxa_ssp_write_reg()
265  * pxa_ssp_read_reg - Read from a SSP register
272 	return __raw_readl(dev->mmio_base + reg);  in pxa_ssp_read_reg()