Lines Matching +full:clkout +full:- +full:clock

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Si5351A/B/C programmable clock generator platform_data.
10  * enum si5351_pll_src - Si5351 pll clock source
12  * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13  * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22  * enum si5351_multisynth_src - Si5351 multisynth clock source
24  * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
25  * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
34  * enum si5351_clkout_src - Si5351 clock output clock source
36  * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37  * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
39  * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
40  * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
51  * enum si5351_drive_strength - Si5351 clock output drive strength
53  * @SI5351_DRIVE_2MA: 2mA clock output drive strength
54  * @SI5351_DRIVE_4MA: 4mA clock output drive strength
55  * @SI5351_DRIVE_6MA: 6mA clock output drive strength
56  * @SI5351_DRIVE_8MA: 8mA clock output drive strength
67  * enum si5351_disable_state - Si5351 clock output disable state
84  * struct si5351_clkout_config - Si5351 clock output configuration
85  * @clkout: clkout number
86  * @multisynth_src: multisynth source clock
87  * @clkout_src: clkout source clock
88  * @pll_master: if true, clkout can also change pll rate
89  * @pll_reset: if true, clkout can reset its pll
91  * @rate: initial clkout rate, or default if 0
104  * struct si5351_platform_data - Platform data for the Si5351 clock driver
105  * @clk_xtal: xtal input clock
106  * @clk_clkin: clkin input clock
107  * @pll_src: array of pll source clock setting
109  * @clkout: array of clkout configuration
114 	struct si5351_clkout_config clkout[8];  member