1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
75 #define NAND_CMD_NONE		-1
84 #define NAND_DATA_IFACE_CHECK_ONLY	-1
87  * Constants for Hardware ECC
89 /* Reset Hardware ECC for read */
91 /* Reset Hardware ECC for write */
93 /* Enable Hardware ECC before syndrome is read back from flash */
98  * ecc.correct() returns -EBADMSG.
124  * Chip requires ready check on read (for auto-incremented sequential read).
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
174  * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175  * on the default ->cmdfunc() implementation, you may want to let the core
185  * to select ECC algorithms supported by the boot ROM or similar restrictions.
208  * Some controllers with pipelined ECC engines override the BBM marker with
209  * data or ECC bytes, thus making bad block detection through bad block marker
225  * struct nand_parameters - NAND generic parameters from the parameter page
249  * struct nand_id - NAND id structure
259  * struct nand_ecc_step_info - ECC step information of ECC engine
260  * @stepsize: data bytes per ECC step
271  * struct nand_ecc_caps - capability of ECC engine
272  * @stepinfos: array of ECC step information
273  * @nstepinfos: number of ECC step information
274  * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
282 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
297  * struct nand_ecc_ctrl - Control structure for ECC
298  * @engine_type: ECC engine type
300  * @algo:	ECC algorithm
301  * @steps:	number of ECC steps per page
302  * @size:	data bytes per ECC step
303  * @bytes:	ECC bytes per step
304  * @strength:	max number of correctible bits per ECC step
305  * @total:	total number of ECC bytes per page
306  * @prepad:	padding information for syndrome based ECC generators
307  * @postpad:	padding information for syndrome based ECC generators
308  * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
309  * @calc_buf:	buffer for calculated ECC, size is oobsize.
310  * @code_buf:	buffer for ECC read from flash, size is oobsize.
311  * @hwctl:	function to control hardware ECC generator. Must only
312  *		be provided if an hardware ECC is available
313  * @calculate:	function for ECC calculation or readback from ECC hardware
314  * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
316  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
317  *		ECC strength, or any other error code if the error is not
319  *		If -EBADMSG is returned the input buffers should be left
321  * @read_page_raw:	function to read a raw page without ECC. This function
322  *			should hide the specific layout used by the ECC
323  *			controller and always return contiguous in-band and
324  *			out-of-band data even if they're not stored
326  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
327  *			out-of-band data).
328  * @write_page_raw:	function to write a raw page without ECC. This function
329  *			should hide the specific layout used by the ECC
331  *			in-band and out-of-band data. ECC controller is
334  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
335  *			out-of-band data).
336  * @read_page:	function to read a page according to the ECC generator
338  *		any single ECC step, -EIO hw error
339  * @read_subpage:	function to read parts of the page covered by ECC;
341  * @write_subpage:	function to write parts of the page covered by ECC.
342  * @write_page:	function to write a page according to the ECC generator
344  * @write_oob_raw:	function to write chip OOB data without ECC
345  * @read_oob_raw:	function to read chip OOB data without ECC
354 	int size;  member
388  * struct nand_sdr_timings - SDR NAND chip timings
393  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf
409  * @tCHZ_max: CE# high to output hi-Z
418  * @tIR_min: Output hi-Z to RE# low
425  * @tRHZ_max: RE# high to output hi-Z
480  * struct nand_nvddr_timings - NV-DDR NAND chip timings
482  * This struct defines the timing requirements of a NV-DDR NAND data interface.
485  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
486  * (chapter 4.18.2 NV-DDR)
511  * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
512  * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
567  * between SDR and NV-DDR, timings related to the internal chip behavior are
569  * the same definition and are shared in both SDR and NV-DDR timing structures:
570  * - tADL_min
571  * - tBERS_max
572  * - tCCS_min
573  * - tFEAT_max
574  * - tPROG_max
575  * - tR_max
576  * - tRR_min
577  * - tRST_max
578  * - tWB_max
584 		nand_get_sdr_timings(conf)->timing_name :	\
585 		nand_get_nvddr_timings(conf)->timing_name
594  * enum nand_interface_type - NAND interface type
604  * struct nand_interface_config - NAND interface timing
623  * nand_interface_is_sdr - get the interface type
628 	return conf->type == NAND_SDR_IFACE;  in nand_interface_is_sdr()
632  * nand_interface_is_nvddr - get the interface type
637 	return conf->type == NAND_NVDDR_IFACE;  in nand_interface_is_nvddr()
641  * nand_get_sdr_timings - get SDR timing from data interface
648 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
650 	return &conf->timings.sdr;  in nand_get_sdr_timings()
654  * nand_get_nvddr_timings - get NV-DDR timing from data interface
661 		return ERR_PTR(-EINVAL);  in nand_get_nvddr_timings()
663 	return &conf->timings.nvddr;  in nand_get_nvddr_timings()
667  * struct nand_op_cmd_instr - Definition of a command instruction
675  * struct nand_op_addr_instr - Definition of an address instruction
685  * struct nand_op_data_instr - Definition of a data instruction
690  * @force_8bit: force 8-bit access
706  * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
714  * enum nand_op_instr_type - Definition of all instruction types
730  * struct nand_op_instr - Instruction object
845  * struct nand_subop - a sub operation
846  * @cs: the CS line to select for this NAND sub-operation
850  *			   of the sub-operation
852  *			of the sub-operation
858  * be split by the parser into sub-operations which will be passed to the
879  * struct nand_op_parser_addr_constraints - Constraints for address instructions
888  * struct nand_op_parser_data_constraints - Constraints for data instructions
896  * struct nand_op_parser_pattern_elem - One element of a pattern
946  * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
949  * @exec: the function that will issue a sub-operation
955  * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
978  * struct nand_op_parser - NAND controller operation parser descriptor
1004  * struct nand_operation - NAND operation descriptor
1007  *		 de-asserted (ERASE, PROG, ...)
1011  * The actual operation structure that will be passed to chip->exec_op().
1043 	switch (instr->type) {  in nand_op_trace()
1046 			 instr->ctx.cmd.opcode);  in nand_op_trace()
1050 			 instr->ctx.addr.naddrs,  in nand_op_trace()
1051 			 instr->ctx.addr.naddrs < 64 ?  in nand_op_trace()
1052 			 instr->ctx.addr.naddrs : 64,  in nand_op_trace()
1053 			 instr->ctx.addr.addrs);  in nand_op_trace()
1057 			 instr->ctx.data.len,  in nand_op_trace()
1058 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1059 			 ", force 8-bit" : "");  in nand_op_trace()
1063 			 instr->ctx.data.len,  in nand_op_trace()
1064 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1065 			 ", force 8-bit" : "");  in nand_op_trace()
1069 			 instr->ctx.waitrdy.timeout_ms);  in nand_op_trace()
1076  * struct nand_controller_ops - Controller operations
1079  *		 flash ID and MTD fields such as erase size, page size and OOB
1080  *		 size have been set up. ECC requirements are available if
1082  *		 choose the appropriate ECC configuration and allocate
1086  *		 nand_controller_ops->attach_chip().
1089  *		 This method replaces chip->legacy.cmdfunc(),
1090  *		 chip->legacy.{read,write}_{buf,byte,word}(),
1091  *		 chip->legacy.dev_ready() and chip->legacy.waitfunc().
1108  * struct nand_controller - Structure used to describe a NAND controller
1112  * @supported_op:	NAND controller known-to-be-supported operations,
1132 	mutex_init(&nfc->lock);  in nand_controller_init()
1136  * struct nand_legacy - NAND chip legacy fields/hooks
1187  * struct nand_chip_ops - NAND chip operations
1192  * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1206  * struct nand_manufacturer - NAND manufacturer structure
1216  * struct nand_secure_region - NAND secure region structure
1218  * @size: Size of the secure region
1222 	u64 size;  member
1226  * struct nand_chip - NAND Private Flash Chip Data
1258  * @pagemask: Page number mask = number of (pages / chip) - 1
1260  * @data_buf: Buffer for data, size is (page size + oobsize)
1264  * @pagecache.page: Page number currently in the cache. -1 means no page is
1271  * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1285  * @ecc: The ECC controller structure
1344 	struct nand_ecc_ctrl ecc;  member
1355 	return &chip->base.mtd;  in nand_to_mtd()
1360 	return chip->priv;  in nand_get_controller_data()
1365 	chip->priv = priv;  in nand_set_controller_data()
1371 	chip->manufacturer.priv = priv;  in nand_set_manufacturer_data()
1376 	return chip->manufacturer.priv;  in nand_get_manufacturer_data()
1391  * nand_get_interface_config - Retrieve the current interface configuration
1398 	return chip->current_interface_config;  in nand_get_interface_config()
1403  * defined the chip, including the geometry (chip size, eraseblock size, page
1404  * size). All these chips have 512 bytes NAND page size.
1411  * A helper for defining newer chips which report their page size and
1412  * eraseblock size via the extended ID bytes.
1416  * device ID now only represented a particular total chip size (and voltage,
1417  * buswidth), and the page size, eraseblock size, and OOB size could vary while
1426 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1427 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1430  * struct nand_flash_dev - NAND Flash Device ID Structure
1431  * @name: a human-readable name of the NAND chip
1438  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1439  *            well as the eraseblock size) is determined from the extended NAND
1441  * @chipsize: total chip size in MiB
1442  * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1445  * @oobsize: OOB size
1446  * @ecc: ECC correctability and step information from the datasheet.
1447  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1449  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1451  *               For example, the "4bit ECC for each 512Byte" can be set with
1472 	} ecc;  member
1484 	WARN(nanddev_bits_per_cell(&chip->base) == 0,  in nand_is_slc()
1485 	     "chip->bits_per_cell is used uninitialized\n");  in nand_is_slc()
1486 	return nanddev_bits_per_cell(&chip->base) == 1;  in nand_is_slc()
1490  * nand_opcode_8bits - Check if the opcode's address should be sent only on the
1523 				void *ecc, int ecclen,
1621  * nand_get_data_buf() - Get the internal page buffer
1624  * Returns the pre-allocated page buffer after invalidating the cache. This
1636 	chip->pagecache.page = -1;  in nand_get_data_buf()
1638 	return chip->data_buf;  in nand_get_data_buf()
1641 /* Parse the gpio-cs property */