Lines Matching +full:0 +full:x442
11 #define SOFT_RESET_CTRL (0x15) /* Specific to FC3W */
12 #define MISC_CTRL (0x14) /* Specific to FC3A */
16 #define DEVICE_ID (0x2)
17 #define DEVICE_ID_MASK (0x1000) /* Bit 12 is 1 if FC3W and 0 if FC3A */
21 #define FOD_0 (0x300)
22 #define FOD_0_VFC3A (0x400)
23 #define FOD_1 (0x340)
24 #define FOD_1_VFC3A (0x440)
25 #define FOD_2 (0x380)
26 #define FOD_2_VFC3A (0x480)
29 #define TDC_CTRL (0x44a) /* Specific to FC3W */
30 #define TDC_ENABLE_CTRL (0x169) /* Specific to FC3A */
31 #define TDC_DAC_CAL_CTRL (0x16a) /* Specific to FC3A */
32 #define TDC_EN BIT(0)
34 #define TDC_DAC_RECAL_REQ_VFC3A BIT(0)
36 #define TDC_FB_DIV_INT_CNFG (0x442)
37 #define TDC_FB_DIV_INT_CNFG_VFC3A (0x162)
38 #define TDC_FB_DIV_INT_MASK GENMASK(7, 0)
39 #define TDC_REF_DIV_CNFG (0x443)
40 #define TDC_REF_DIV_CNFG_VFC3A (0x163)
41 #define TDC_REF_DIV_CONFIG_MASK GENMASK(2, 0)
44 #define TIME_CLOCK_SRC (0xa01) /* Specific to FC3W */
45 #define TIME_CLOCK_COUNT (0xa00) /* Specific to FC3W */
46 #define TIME_CLOCK_COUNT_MASK GENMASK(5, 0)
48 #define SUB_SYNC_GEN_CNFG (0xa04)
50 #define TOD_COUNTER_READ_REQ (0xa5f)
51 #define TOD_COUNTER_READ_REQ_VFC3A (0x6df)
52 #define TOD_SYNC_LOAD_VAL_CTRL (0xa10)
53 #define TOD_SYNC_LOAD_VAL_CTRL_VFC3A (0x690)
54 #define SYNC_COUNTER_MASK GENMASK_ULL(51, 0)
55 #define SUB_SYNC_COUNTER_MASK GENMASK(30, 0)
56 #define TOD_SYNC_LOAD_REQ_CTRL (0xa21)
57 #define TOD_SYNC_LOAD_REQ_CTRL_VFC3A (0x6a1)
59 #define SUB_SYNC_LOAD_ENABLE BIT(0)
60 #define SYNC_LOAD_REQ BIT(0)
62 #define LPF_MODE_CNFG (0xa80)
63 #define LPF_MODE_CNFG_VFC3A (0x700)
65 LPF_DISABLED = 0,
71 #define LPF_CTRL (0xa98)
72 #define LPF_CTRL_VFC3A (0x718)
73 #define LPF_EN BIT(0)
75 #define LPF_BW_CNFG (0xa81)
77 #define LPF_BW_MULT GENMASK(2, 0)
78 #define LPF_BW_SHIFT_DEFAULT (0xb)
79 #define LPF_BW_MULT_DEFAULT (0x0)
80 #define LPF_BW_SHIFT_1PPS (0x5)
82 #define LPF_WR_PHASE_CTRL (0xaa8)
83 #define LPF_WR_PHASE_CTRL_VFC3A (0x728)
84 #define LPF_WR_FREQ_CTRL (0xab0)
85 #define LPF_WR_FREQ_CTRL_VFC3A (0x730)
87 #define TIME_CLOCK_TDC_FANOUT_CNFG (0xB00)
88 #define TIME_SYNC_TO_TDC_EN BIT(0)
92 REF0 = 0,
104 #define TIME_CLOCK_MEAS_CNFG (0xB04)
105 #define TDC_MEAS_MODE BIT(0)
107 CONTINUOUS = 0,
112 #define TIME_CLOCK_MEAS_DIV_CNFG (0xB08)
115 #define TIME_CLOCK_MEAS_CTRL (0xB10)
116 #define TDC_MEAS_EN BIT(0)
119 #define TDC_FIFO_READ_REQ (0xB2F)
120 #define TDC_FIFO_READ (0xB30)
122 #define FINE_MEAS_MASK GENMASK(12, 0)
124 #define TDC_FIFO_CTRL (0xB12)
125 #define FIFO_CLEAR BIT(0)
126 #define TDC_FIFO_STS (0xB38)
128 #define FIFO_EMPTY BIT(0)
129 #define TDC_FIFO_EVENT (0xB39)
138 #define DPLL_STS (0x580)
139 #define DPLL_STS_VFC3A (0x571)
140 #define DPLL_STATE_STS_MASK (0x70)
142 #define DPLL_REF_SEL_STS_MASK (0x6)
145 #define DPLL_REF_PRIORITY_CNFG (0x502)
146 #define DPLL_REFX_PRIORITY_DISABLE_MASK (0xf)
147 #define DPLL_REF0_PRIORITY_ENABLE_AND_SET_MASK (0x31)
148 #define DPLL_REF1_PRIORITY_ENABLE_AND_SET_MASK (0xc2)
149 #define DPLL_REF2_PRIORITY_ENABLE_AND_SET_MASK (0x304)
150 #define DPLL_REF3_PRIORITY_ENABLE_AND_SET_MASK (0xc08)
157 DPLL_STATE_MIN = 0,
168 #define LOSMON_STS_0 (0x81e)
169 #define LOSMON_STS_0_VFC3A (0x18e)
170 #define LOSMON_STS_1 (0x82e)
171 #define LOSMON_STS_1_VFC3A (0x19e)
172 #define LOSMON_STS_2 (0x83e)
173 #define LOSMON_STS_2_VFC3A (0x1ae)
174 #define LOSMON_STS_3 (0x84e)
175 #define LOSMON_STS_3_VFC3A (0x1be)
176 #define LOS_STS_MASK (0x1)
178 #define FREQMON_STS_0 (0x874)
179 #define FREQMON_STS_0_VFC3A (0x1d4)
180 #define FREQMON_STS_1 (0x894)
181 #define FREQMON_STS_1_VFC3A (0x1f4)
182 #define FREQMON_STS_2 (0x8b4)
183 #define FREQMON_STS_2_VFC3A (0x214)
184 #define FREQMON_STS_3 (0x8d4)
185 #define FREQMON_STS_3_VFC3A (0x234)
189 #define TIME_CLK_FREQ_ADDR (0xffa0)
190 #define XTAL_FREQ_ADDR (0xffa1)
198 V_DEFAULT = 0,
205 FREQ_MIN = 0,
270 return 0; in idtfc3_set_hw_param()