Lines Matching +full:0 +full:x103
10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
13 #define DPLL1_TOD_CNFG 0x134
14 #define DPLL2_TOD_CNFG 0x1B4
16 #define DPLL1_TOD_STS 0x10B
17 #define DPLL2_TOD_STS 0x18B
19 #define DPLL1_TOD_TRIGGER 0x115
20 #define DPLL2_TOD_TRIGGER 0x195
22 #define DPLL1_OPERATING_MODE_CNFG 0x120
23 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
25 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
26 #define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
28 #define DPLL1_PHASE_OFFSET_CNFG 0x143
29 #define DPLL2_PHASE_OFFSET_CNFG 0x1C3
31 #define DPLL1_SYNC_EDGE_CNFG 0x140
32 #define DPLL2_SYNC_EDGE_CNFG 0x1C0
34 #define DPLL1_INPUT_MODE_CNFG 0x116
35 #define DPLL2_INPUT_MODE_CNFG 0x196
37 #define DPLL1_OPERATING_STS 0x102
38 #define DPLL2_OPERATING_STS 0x182
40 #define DPLL1_CURRENT_FREQ_STS 0x103
41 #define DPLL2_CURRENT_FREQ_STS 0x183
43 #define REG_SOFT_RESET 0X381
45 #define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
46 #define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
54 #define PLL_MODE_SHIFT (0)
55 #define PLL_MODE_MASK (0x1F)
58 #define COMBO_MODE_MASK (0x3)
61 #define OPERATING_STS_MASK (0x7)
62 #define OPERATING_STS_SHIFT (0x0)
65 #define READ_TRIGGER_MASK (0xF)
66 #define READ_TRIGGER_SHIFT (0x0)
67 #define WRITE_TRIGGER_MASK (0xF0)
68 #define WRITE_TRIGGER_SHIFT (0x4)
74 PLL_MODE_MIN = 0,
88 HW_TOD_TRIG_SEL_MIN = 0,