Lines Matching +full:block +full:- +full:fetch

1 /* SPDX-License-Identifier: GPL-2.0 */
15  * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
22  * To support 2-stage tansfer, we must configure the channel mode and trigger
27  * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
29  * support the 2-stage transfer.
35  * Now the DMA controller can supports 2 groups 2-stage transfer.
46  * enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
52  * automatically once the source channel's block request is done.
56  * automatically once the source channel's link-list request is done.
69  * @SPRD_DMA_BLK_REQ: block request mode
71  * @SPRD_DMA_LIST_REQ: link-list request mode
73  * We have 4 types request mode: fragment mode, block mode, transaction mode
74  * and linklist mode. One transaction can contain several blocks, one block can
75  * contain several fragments. Link-list mode means we can save several DMA
76  * configuration into one reserved memory, then DMA can fetch each DMA
91  * @SPRD_DMA_BLK_INT: block done interrupt when one block request is done.
92  * @SPRD_DMA_BLK_FRAG_INT: block and fragment interrupt when one fragment
93  * or one block request is done.
98  * @SPRD_DMA_TRANS_BLK_INT: transaction and block interrupt when one
99  * transaction request or block request is done.
100  * @SPRD_DMA_LIST_INT: link-list done interrupt when one link-list request
118  * struct sprd_dma_linklist - DMA link-list address structure
119  * @virt_addr: link-list virtual address to configure link-list node
120  * @phy_addr: link-list physical address to link DMA transfer
121  * @wrap_addr: the wrap address for link-list mode, which means once the
125  * The Spreadtrum DMA controller supports the link-list mode, that means slaves
129  * link-list register.
131  * Just as shown below, the link-list pointer register will be pointed to the
132  * physical address of 'configuration 1', and the 'configuration 1' link-list
139  * Note: The last link-list pointer should point to the physical address
144  * ======================             -----------------------
145  *|                      |           |    configuration 1    |<---
146  *|   DMA controller     |   ------->|                       |   |
150  *| linklist pointer reg |----   ----|    linklist pointer   |   |
151  * ======================        |    -----------------------    |
153  *                               |    -----------------------    |
155  *                               --->|                       |   |
159  *                               ----|    linklist pointer   |   |
160  *                               |    -----------------------    |
162  *                               |    -----------------------    |
164  *                               --->|                       |   |
171  *                               |    -----------------------    |
173  *                               --->|                       |   |
177  *                                   |    linklist pointer   |----
178  *                                    -----------------------
180  * To support the link-list mode, DMA slaves should allocate one segment memory
181  * from always-on IRAM or dma coherent memory to store these groups of DMA