Lines Matching +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
25 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
26 …MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
27 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
28 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
29 #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
34 #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
35 #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
36 #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
57 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
59 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
71 #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
72 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
84 #define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */
93 #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
95 #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
99 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
109 #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
129 #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
133 #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
136 #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
137 #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
138 #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
141 #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
146 #define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */
172 #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */
174 #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
178 #define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
183 #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
188 #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
190 #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
209 #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
221 #define AT91_PMC_LPM BIT(20) /* Low-power Mode */
240 #define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */
242 #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/