Lines Matching +full:power +full:- +full:gate

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
20 /** @brief output of gate CLK_ENB_APB2APE */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
34 /** @brief output of gate CLK_ENB_CAN2_HOST */
46 /** @brief output of gate CLK_ENB_DPAUX */
78  * throughput and memory controller power.
85 /** @brief output of gate CLK_ENB_EQOS_RX */
97 /** @brief output of gate CLK_ENB_FUSE */
154 /** @brief output of gate CLK_ENB_MIPI_CAL */
158 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
160 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
162 /** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */
164 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
166 /** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */
168 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
256 /** @brief output of gate CLK_ENB_SOR_SAFE */
314 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */
322 /** @brief output of gate CLK_ENB_USB2_TRK */
334 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */
336 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */
338 /** @brief output of gate CLK_ENB_PEX2_CORE_9 */
362 /** @brief output of gate CLK_ENB_PEX2_CORE_10 */
418 /** @brief AXI_CBB branch sharing gate control with SDMMC4 */
422 /** @brief output of gate CLK_ENB_PEX0_CORE_0 */
424 /** @brief output of gate CLK_ENB_PEX0_CORE_1 */
426 /** @brief output of gate CLK_ENB_PEX0_CORE_2 */
428 /** @brief output of gate CLK_ENB_PEX0_CORE_3 */
430 /** @brief output of gate CLK_ENB_PEX0_CORE_4 */
432 /** @brief output of gate CLK_ENB_PEX1_CORE_5 */
533 /** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */
567 /** @brief output of gate CLK_ENB_BPMP_CPU */
589 /** @brief GBE PLL hardware power sequencer */
599 /** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */
601 /** @brief CLK_ENB_PLLREFE_OUT gate output */
637 /** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */
697 /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
699 /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
701 /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
703 /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
715 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
717 /** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */
719 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
721 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
733 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
735 /** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */
737 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
739 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
751 /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
753 /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
755 /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
757 /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
769 /** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */
771 /** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */
810 /** @brief output of gate CLK_ENB_SCE_CPU */
812 /** @brief output of gate CLK_ENB_RCE_CPU */
814 /** @brief output of gate CLK_ENB_DCE_CPU */