Lines Matching +full:mux +full:- +full:clock

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9  * @defgroup bpmp_clock_ids Clock ID's
12 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */
18 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
32 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
38 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
40 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
42 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
44 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
48 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */
51  * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY
58 /** @brief clock recovered from EAVB input */
68 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
70 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
73  * @brief controls the EMC clock frequency.
74  * @details Doing a clk_set_rate on this clock will select the
75  * appropriate clock source, program the source rate and execute a
76  * specific sequence to switch to the new clock source for both memory
89 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
91 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
93 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
95 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
103 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
104 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
108 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
110 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
112 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
114 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
116 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
118 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
120 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
122 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
124 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
126 /** @brief clock recovered from I2S1 input */
128 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
130 /** @brief clock recovered from I2S2 input */
132 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
134 /** @brief clock recovered from I2S3 input */
136 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
138 /** @brief clock recovered from I2S4 input */
140 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
142 /** @brief clock recovered from I2S5 input */
144 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
146 /** @brief clock recovered from I2S6 input */
148 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
150 /** @brief Monitored branch of EQOS_RX clock */
172 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
174 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
176 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
188 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
190 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
210 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
212 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
214 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
216 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
218 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
220 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
222 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
224 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
232 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
236 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
240 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
246 /** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */
252 /** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */
260 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
262 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
264 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
266 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */
268 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
270 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
272 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
274 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
276 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
278 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
280 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
282 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
284 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
286 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
288 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
290 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
292 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
296 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */
298 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
300 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */
302 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
304 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
306 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
308 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
310 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
312 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
316 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
318 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
320 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
324 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
326 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
332 /** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */
348 /** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */
350 /** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */
352 /** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */
354 /** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */
356 /** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */
358 /** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */
382 /** @brief NAFLL clock source for BPMP */
384 /** @brief NAFLL clock source for SCE */
386 /** @brief NAFLL clock source for NVDEC */
388 /** @brief NAFLL clock source for NVJPG */
390 /** @brief NAFLL clock source for TSEC */
392 /** @brief NAFLL clock source for VI */
394 /** @brief NAFLL clock source for SE */
396 /** @brief NAFLL clock source for NVENC */
398 /** @brief NAFLL clock source for ISP */
400 /** @brief NAFLL clock source for VIC */
402 /** @brief NAFLL clock source for AXICBB */
404 /** @brief NAFLL clock source for NVJPG1 */
406 /** @brief NAFLL clock source for PVA core */
408 /** @brief NAFLL clock source for PVA VPS */
412 /** @brief NAFLL clock source for RCE */
434 /** @brief Monitored branch of PEX0_C0_CORE clock */
436 /** @brief Monitored branch of PEX0_C1_CORE clock */
438 /** @brief Monitored branch of PEX0_C2_CORE clock */
440 /** @brief Monitored branch of PEX0_C3_CORE clock */
442 /** @brief Monitored branch of PEX0_C4_CORE clock */
444 /** @brief Monitored branch of PEX1_C5_CORE clock */
446 /** @brief Monitored branch of PEX1_C6_CORE clock */
456 /** @brief output of the mux controlled by PLLC4_CLK_SEL */
462 /** @brief Monitored branch of PEX2_C7_CORE clock */
464 /** @brief Monitored branch of PEX2_C8_CORE clock */
466 /** @brief Monitored branch of PEX2_C9_CORE clock */
468 /** @brief Monitored branch of PEX2_C10_CORE clock */
470 /** @brief RX clock recovered from MGBE0 lane input */
472 /** @brief RX clock recovered from MGBE1 lane input */
474 /** @brief RX clock recovered from MGBE2 lane input */
476 /** @brief RX clock recovered from MGBE3 lane input */
518 /** @brief NAFLL clock source for CPU cluster 0 */
521 /** @brief NAFLL clock source for CPU cluster 1 */
524 /** @brief NAFLL clock source for CPU cluster 2 */
537 /** @brief 32K input clock provided by PMIC */
539 /** @brief Fixed 48MHz clock divided down from utmipll */
541 /** @brief Fixed 480MHz clock divided down from utmipll */
557 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
559 /** @brief GPU system clock */
561 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */
571 /** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */
573 /** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */
575 /** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */
577 /** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */
585 /** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */
611 /** @brief NAFLL clock source for OFA */
615 /** @brief NAFLL clock source for SEU1 */
619 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
621 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */
623 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */
627 /** @brief NAFLL clock source for DCE */
629 /** @brief Monitored branch of MPHY_L0_RX_ANA clock */
631 /** @brief Monitored branch of MPHY_L1_RX_ANA clock */
633 /** @brief ungated version of TX symbol clock after fixed 1/2 divider */
643 /** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
645 /** @brief Monitored branch of MPHY_L0_TX_SYMB clock */
653 /** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
655 /** @brief Monitored branch of MPHY_L0_RX_SYMB clock */
657 /** @brief Monitored branch of MBGE0 RX input clock */
659 /** @brief Monitored branch of MBGE1 RX input clock */
661 /** @brief Monitored branch of MBGE2 RX input clock */
663 /** @brief Monitored branch of MBGE3 RX input clock */
665 /** @brief Monitored branch of MGBE0 RX PCS mux output */
667 /** @brief Monitored branch of MGBE1 RX PCS mux output */
669 /** @brief Monitored branch of MGBE2 RX PCS mux output */
671 /** @brief Monitored branch of MGBE3 RX PCS mux output */
673 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */
681 /** @brief RX PCS clock recovered from MGBE0 lane input */
683 /** @brief RX PCS clock recovered from MGBE1 lane input */
685 /** @brief RX PCS clock recovered from MGBE2 lane input */
687 /** @brief RX PCS clock recovered from MGBE3 lane input */
689 /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
707 /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
725 /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
743 /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
777 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */
779 /** @brief clock recovered from I2S7 input */
781 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */
783 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */
785 /** @brief Monitored output of I2S7 pad macro mux */
787 /** @brief clock recovered from I2S8 input */
789 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */
791 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */
793 /** @brief Monitored output of I2S8 pad macro mux */
795 /** @brief NAFLL clock source for GPU GPC0 */
797 /** @brief NAFLL clock source for GPU GPC1 */
799 /** @brief NAFLL clock source for GPU SYSCLK */
801 /** @brief NAFLL clock source for CPU cluster 0 DSUCLK */
804 /** @brief NAFLL clock source for CPU cluster 1 DSUCLK */
807 /** @brief NAFLL clock source for CPU cluster 2 DSUCLK */
842 /** @brief VPLL0 reference clock */
866 /** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */
868 /** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */
870 /** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */
874 /** @brief Link clock input from DP macro brick PLL */
876 /** @brief SOR AFIFO clock outut */