Lines Matching +full:pll +full:- +full:clock +full:- +full:frequency

1 /* SPDX-License-Identifier: GPL-2.0 */
8  * @defgroup clock_ids Clock Identifiers
235  *   @defgroup nafll_clks NAFLL clock sources
355  * pwrclk. @warning: This is almost certainly not the clock you think
356  * it is. If you're looking for the clock of the graphics engine, see
417  * @brief controls the EMC clock frequency.
418  * @details Doing a clk_set_rate on this clock will select the
419  * appropriate clock source, program the source rate and execute a
420  * specific sequence to switch to the new clock source for both memory
677 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read…
742   *      * VCO/pdiv defined by this clock object
751 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
759 /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is T…
761 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
763 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
779 /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE vol…
783  * @details This clock only has enable and disable methods. When the
791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
797 /** @brief fixed /5 divider.  Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used a…
809 …DQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
813 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enab…
818  * @brief GPC2CLK-div-2
819  * @details fixed /2 divider. Output frequency is
820  * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
821  * frequency at which the GPU graphics engine runs. */
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
829 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
835 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
837 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
840  * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
841  * @details Note that this clock only controls the VCO output, before
842  * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
846 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
848 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
852 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
854 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
856 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
858 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
860 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
862 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
864 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain …
866 /** Fixed frequency 960MHz PLL for USB and EAVB */
868 /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
870 /** @brief NAFLL clock source for AXI_CBB */
872 /** @brief NAFLL clock source for BPMP */
874 /** @brief NAFLL clock source for ISP */
876 /** @brief NAFLL clock source for NVDEC */
878 /** @brief NAFLL clock source for NVENC */
880 /** @brief NAFLL clock source for NVJPG */
882 /** @brief NAFLL clock source for SCE */
884 /** @brief NAFLL clock source for SE */
886 /** @brief NAFLL clock source for TSEC */
888 /** @brief NAFLL clock source for TSECB */
890 /** @brief NAFLL clock source for VI */
892 /** @brief NAFLL clock source for VIC */
894 /** @brief NAFLL clock source for DISP */
896 /** @brief NAFLL clock source for GPU */
898 /** @brief NAFLL clock source for M-CPU cluster */
900 /** @brief NAFLL clock source for B-CPU cluster */
910 /** @brief clock recovered from EAVB input */
912 /** @brief clock recovered from DTV input */
918 /** @brief clock recovered from I2S1 input */
920 /** @brief clock recovered from I2S2 input */
922 /** @brief clock recovered from I2S3 input */
924 /** @brief clock recovered from I2S4 input */
926 /** @brief clock recovered from I2S5 input */
928 /** @brief clock recovered from I2S6 input */
930 /** @brief clock recovered from SPDIFIN input */
935  * @details maximum clock identifier value plus one.