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39 #define CLK_MOUT_SCLK_MMC0_D 35
236 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
430 #define CLK_SCLK_UART1 35
500 #define CLK_SCLK_TMU0 35
543 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
677 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35
797 #define CLK_PCLK_AUD_I2S 35
952 #define CLK_HCLK_CSSYS 35
1072 #define CLK_ACLK_SMMU_DIS0 35
1153 #define CLK_DIV_PCLK_LITE_B 35
1290 #define CLK_ACLK_ASYNCAXIM_CA5 35
1371 #define CLK_PCLK_SLIMSSS 35