Lines Matching +full:- +full:only

1 /* SPDX-License-Identifier: GPL-2.0 */
29 #define CLK_MOUT_MPLL_USER_T	17 /* Exynos4x12 only */
30 #define CLK_MOUT_MPLL_USER_C	18 /* Exynos4x12 only */
54 #define CLK_SCLK_MDNIE0		141 /* Exynos4412 only */
63 #define CLK_SCLK_SATA		150 /* Exynos4210 only */
76 #define CLK_SCLK_FIMD1		163 /* Exynos4210 only */
77 #define CLK_SCLK_MIPI1		164 /* Exynos4210 only */
82 #define CLK_SCLK_MIPIHSI	169 /* Exynos4412 only */
86 #define CLK_SCLK_PWM_ISP	173 /* Exynos4x12 only */
87 #define CLK_SCLK_SPI0_ISP	174 /* Exynos4x12 only */
88 #define CLK_SCLK_SPI1_ISP	175 /* Exynos4x12 only */
89 #define CLK_SCLK_UART_ISP	176 /* Exynos4x12 only */
108 #define CLK_TVENC		270 /* Exynos4210 only */
123 #define CLK_MDNIE0		285 /* Exynos4412 only */
126 #define CLK_FIMD1		288 /* Exynos4210 only */
127 #define CLK_MIE1		289 /* Exynos4210 only */
128 #define CLK_DSIM1		290 /* Exynos4210 only */
129 #define CLK_SMMU_FIMD1		291 /* Exynos4210 only */
133 #define CLK_SATA_PHY		295 /* Exynos4210 only */
140 #define CLK_SATA		302 /* Exynos4210 only */
187 #define CLK_MIPI_HSI		349 /* Exynos4210 only */
190 #define CLK_ASYNC_G3D		353 /* Exynos4x12 only */
191 #define CLK_PWM_ISP_SCLK	379 /* Exynos4x12 only */
192 #define CLK_SPI0_ISP_SCLK	380 /* Exynos4x12 only */
193 #define CLK_SPI1_ISP_SCLK	381 /* Exynos4x12 only */
194 #define CLK_UART_ISP_SCLK	382 /* Exynos4x12 only */
209 #define CLK_ACLK400_MCUISP	395 /* Exynos4x12 only */
214 /* gate clocks - ppmu */
224 #define CLK_PPMULCD1		409 /* Exynos4210 only */
233 #define CLK_DIV_ACLK200		454 /* Exynos4x12 only */
234 #define CLK_DIV_ACLK400_MCUISP	455 /* Exynos4x12 only */
237 #define CLK_DIV_C2C		458 /* Exynos4x12 only */