Lines Matching +full:hardware +full:- +full:protected

28 #include <linux/dma-fence.h>
36 * DRM_SCHED_FENCE_DONT_PIPELINE - Prevent dependency pipelining
45 * DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT - A fence deadline hint has been set
74 /* Used to choose between FIFO and RR job-scheduling */
81 * struct drm_sched_entity - A wrapper around a job queue (typically
84 * Entities will emit jobs in order to their corresponding hardware
95 * Protected by &drm_sched_rq.lock of @rq.
102 * Lock protecting the run-queue (@rq) to which this entity belongs,
112 * FIXME: Locking is very unclear for this. Writers are protected by
147 * drm_sched_entity_set_priority(). Protected by @lock.
245 * struct drm_sched_rq - queue of entities to be scheduled.
261 /* Following members are protected by the @lock: */
268 * struct drm_sched_fence - fences corresponding to the scheduling of a job.
297 * when scheduling the job on hardware. We signal the
319 * struct drm_sched_job - A job to be run by an entity.
393 return s_job && atomic_inc_return(&s_job->karma) > threshold; in drm_sched_invalidate_job()
403 * struct drm_sched_backend_ops - Define the backend operations
441 * nothing is queued while we reset the hardware queue
442 * 2. Try to gracefully stop non-faulty jobs (optional)
443 * 3. Issue a GPU reset (driver-specific)
444 * 4. Re-submit jobs using drm_sched_resubmit_jobs()
448 * Note that some GPUs have distinct hardware queues but need to reset
458 * 2. Try to gracefully stop non-faulty jobs on all queues impacted by
460 * 3. Issue a GPU reset on all faulty queues (driver-specific)
461 * 4. Re-submit jobs on all schedulers impacted by the reset using
485 * pushed to the hardware. Drivers may use this to dynamically update
495 * struct drm_gpu_scheduler - scheduler instance-specific data
502 * @num_rqs: Number of run-queues. This is at most DRM_SCHED_PRIORITY_COUNT,
503 * as there's usually one run-queue per priority, but could be less.
504 * @sched_rq: An allocated array of run-queues of size @num_rqs;
527 * One scheduler is implemented for each hardware ring.