199 	const struct s3c2410_wdt_variant *drv_data;  member
420 	const u32 mask_val = BIT(wdt->drv_data->mask_bit);  in s3c2410wdt_disable_wdt_reset()
424 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg,  in s3c2410wdt_disable_wdt_reset()
434 	const u32 mask_val = BIT(wdt->drv_data->mask_bit);  in s3c2410wdt_mask_wdt_reset()
435 	const bool val_inv = wdt->drv_data->mask_reset_inv;  in s3c2410wdt_mask_wdt_reset()
439 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,  in s3c2410wdt_mask_wdt_reset()
449 	const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit);  in s3c2410wdt_enable_counter()
453 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg,  in s3c2410wdt_enable_counter()
465 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {  in s3c2410wdt_enable()
471 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) {  in s3c2410wdt_enable()
477 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) {  in s3c2410wdt_enable()
491 	if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))  in s3c2410wdt_mask_dbgack()
672 	if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)  in s3c2410wdt_irq()
683 	if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT))  in s3c2410wdt_get_bootstatus()
686 	ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);  in s3c2410wdt_get_bootstatus()
689 	else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))  in s3c2410wdt_get_bootstatus()
746 	wdt->drv_data = variant;  in s3c2410_get_wdt_drv_data()
775 	if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {  in s3c2410wdt_probe()