1 // SPDX-License-Identifier: GPL-2.0-or-later
84  * DOC: Quirk flags for different Samsung watchdog IP-cores
89  * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
96  * write-only, writing any values to this register clears the interrupt, but
153  * struct s3c2410_wdt_variant - Per-variant config data
337 	{ .compatible = "google,gs101-wdt",
339 	{ .compatible = "samsung,s3c2410-wdt",
341 	{ .compatible = "samsung,s3c6410-wdt",
343 	{ .compatible = "samsung,exynos5250-wdt",
345 	{ .compatible = "samsung,exynos5420-wdt",
347 	{ .compatible = "samsung,exynos7-wdt",
349 	{ .compatible = "samsung,exynos850-wdt",
351 	{ .compatible = "samsung,exynosautov9-wdt",
353 	{ .compatible = "samsung,exynosautov920-wdt",
362 		.name = "s3c2410-wdt",
373 	return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk);  in s3c2410wdt_get_freq()
386 	const u32 mask_val = BIT(wdt->drv_data->mask_bit);  in s3c2410wdt_disable_wdt_reset()
390 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg,  in s3c2410wdt_disable_wdt_reset()
393 		dev_err(wdt->dev, "failed to update reg(%d)\n", ret);  in s3c2410wdt_disable_wdt_reset()
400 	const u32 mask_val = BIT(wdt->drv_data->mask_bit);  in s3c2410wdt_mask_wdt_reset()
401 	const bool val_inv = wdt->drv_data->mask_reset_inv;  in s3c2410wdt_mask_wdt_reset()
405 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,  in s3c2410wdt_mask_wdt_reset()
408 		dev_err(wdt->dev, "failed to update reg(%d)\n", ret);  in s3c2410wdt_mask_wdt_reset()
415 	const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit);  in s3c2410wdt_enable_counter()
419 	ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg,  in s3c2410wdt_enable_counter()
422 		dev_err(wdt->dev, "failed to update reg(%d)\n", ret);  in s3c2410wdt_enable_counter()
431 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {  in s3c2410wdt_enable()
437 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) {  in s3c2410wdt_enable()
443 	if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) {  in s3c2410wdt_enable()
457 	if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))  in s3c2410wdt_mask_dbgack()
460 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_mask_dbgack()
462 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_mask_dbgack()
470 	spin_lock_irqsave(&wdt->lock, flags);  in s3c2410wdt_keepalive()
471 	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);  in s3c2410wdt_keepalive()
472 	spin_unlock_irqrestore(&wdt->lock, flags);  in s3c2410wdt_keepalive()
481 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);  in __s3c2410wdt_stop()
483 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);  in __s3c2410wdt_stop()
491 	spin_lock_irqsave(&wdt->lock, flags);  in s3c2410wdt_stop()
493 	spin_unlock_irqrestore(&wdt->lock, flags);  in s3c2410wdt_stop()
504 	spin_lock_irqsave(&wdt->lock, flags);  in s3c2410wdt_start()
508 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_start()
519 	dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",  in s3c2410wdt_start()
520 		wdt->count, wtcon);  in s3c2410wdt_start()
522 	writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);  in s3c2410wdt_start()
523 	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);  in s3c2410wdt_start()
524 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_start()
525 	spin_unlock_irqrestore(&wdt->lock, flags);  in s3c2410wdt_start()
540 		return -EINVAL;  in s3c2410wdt_set_heartbeat()
545 	dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",  in s3c2410wdt_set_heartbeat()
557 			dev_err(wdt->dev, "timeout %d too big\n", timeout);  in s3c2410wdt_set_heartbeat()
558 			return -EINVAL;  in s3c2410wdt_set_heartbeat()
562 	dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",  in s3c2410wdt_set_heartbeat()
566 	wdt->count = count;  in s3c2410wdt_set_heartbeat()
568 	/* update the pre-scaler */  in s3c2410wdt_set_heartbeat()
569 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_set_heartbeat()
571 	wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);  in s3c2410wdt_set_heartbeat()
573 	writel(count, wdt->reg_base + S3C2410_WTDAT);  in s3c2410wdt_set_heartbeat()
574 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_set_heartbeat()
576 	wdd->timeout = (count * divisor) / freq;  in s3c2410wdt_set_heartbeat()
585 	void __iomem *wdt_base = wdt->reg_base;  in s3c2410wdt_restart()
634 	dev_info(wdt->dev, "watchdog timer expired (irq)\n");  in s3c2410wdt_irq()
636 	s3c2410wdt_keepalive(&wdt->wdt_device);  in s3c2410wdt_irq()
638 	if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)  in s3c2410wdt_irq()
639 		writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);  in s3c2410wdt_irq()
649 	if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT))  in s3c2410wdt_get_bootstatus()
652 	ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);  in s3c2410wdt_get_bootstatus()
654 		dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");  in s3c2410wdt_get_bootstatus()
655 	else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))  in s3c2410wdt_get_bootstatus()
665 	struct device *dev = &pdev->dev;  in s3c2410_get_wdt_drv_data()
671 			   platform_get_device_id(pdev)->driver_data;  in s3c2410_get_wdt_drv_data()
683 		err = of_property_read_u32(dev->of_node,  in s3c2410_get_wdt_drv_data()
684 					   "samsung,cluster-index", &index);  in s3c2410_get_wdt_drv_data()
686 			return dev_err_probe(dev, -EINVAL, "failed to get cluster index\n");  in s3c2410_get_wdt_drv_data()
702 			return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);  in s3c2410_get_wdt_drv_data()
707 	wdt->drv_data = variant;  in s3c2410_get_wdt_drv_data()
718 	struct device *dev = &pdev->dev;  in s3c2410wdt_probe()
726 		return -ENOMEM;  in s3c2410wdt_probe()
728 	wdt->dev = dev;  in s3c2410wdt_probe()
729 	spin_lock_init(&wdt->lock);  in s3c2410wdt_probe()
730 	wdt->wdt_device = s3c2410_wdd;  in s3c2410wdt_probe()
736 	if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {  in s3c2410wdt_probe()
737 		wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,  in s3c2410wdt_probe()
738 						"samsung,syscon-phandle");  in s3c2410wdt_probe()
739 		if (IS_ERR(wdt->pmureg))  in s3c2410wdt_probe()
740 			return dev_err_probe(dev, PTR_ERR(wdt->pmureg),  in s3c2410wdt_probe()
749 	wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);  in s3c2410wdt_probe()
750 	if (IS_ERR(wdt->reg_base))  in s3c2410wdt_probe()
751 		return PTR_ERR(wdt->reg_base);  in s3c2410wdt_probe()
753 	wdt->bus_clk = devm_clk_get_enabled(dev, "watchdog");  in s3c2410wdt_probe()
754 	if (IS_ERR(wdt->bus_clk))  in s3c2410wdt_probe()
755 		return dev_err_probe(dev, PTR_ERR(wdt->bus_clk), "failed to get bus clock\n");  in s3c2410wdt_probe()
758 	 * "watchdog_src" clock is optional; if it's not present -- just skip it  in s3c2410wdt_probe()
761 	wdt->src_clk = devm_clk_get_optional_enabled(dev, "watchdog_src");  in s3c2410wdt_probe()
762 	if (IS_ERR(wdt->src_clk))  in s3c2410wdt_probe()
763 		return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source clock\n");  in s3c2410wdt_probe()
765 	wdt->wdt_device.min_timeout = 1;  in s3c2410wdt_probe()
766 	wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt);  in s3c2410wdt_probe()
768 	watchdog_set_drvdata(&wdt->wdt_device, wdt);  in s3c2410wdt_probe()
773 	watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);  in s3c2410wdt_probe()
774 	ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,  in s3c2410wdt_probe()
775 					wdt->wdt_device.timeout);  in s3c2410wdt_probe()
777 		ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,  in s3c2410wdt_probe()
787 			       pdev->name, pdev);  in s3c2410wdt_probe()
791 	watchdog_set_nowayout(&wdt->wdt_device, nowayout);  in s3c2410wdt_probe()
792 	watchdog_set_restart_priority(&wdt->wdt_device, 128);  in s3c2410wdt_probe()
794 	wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);  in s3c2410wdt_probe()
795 	wdt->wdt_device.parent = dev;  in s3c2410wdt_probe()
800 	 * If "tmr_atboot" param is non-zero, start the watchdog right now. Also  in s3c2410wdt_probe()
808 		s3c2410wdt_start(&wdt->wdt_device);  in s3c2410wdt_probe()
809 		set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);  in s3c2410wdt_probe()
811 		s3c2410wdt_stop(&wdt->wdt_device);  in s3c2410wdt_probe()
814 	ret = devm_watchdog_register_device(dev, &wdt->wdt_device);  in s3c2410wdt_probe()
830 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_probe()
845 	s3c2410wdt_stop(&wdt->wdt_device);  in s3c2410wdt_shutdown()
854 	wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_suspend()
855 	wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);  in s3c2410wdt_suspend()
862 	s3c2410wdt_stop(&wdt->wdt_device);  in s3c2410wdt_suspend()
873 	writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);  in s3c2410wdt_resume()
874 	writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */  in s3c2410wdt_resume()
875 	writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);  in s3c2410wdt_resume()
882 		(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");  in s3c2410wdt_resume()
895 		.name	= "s3c2410-wdt",