1 // SPDX-License-Identifier: GPL-2.0
3  * Renesas RZ/V2H(P) WDT Watchdog Driver
19 #define WDTRR			0x00	/* WDT Refresh Register RW, 8  */
20 #define WDTCR			0x02	/* WDT Control Register RW, 16 */
21 #define WDTSR			0x04	/* WDT Status Register RW, 16 */
22 #define WDTRCR			0x06	/* WDT Reset Control Register RW, 8  */
45 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
61 	 * The down-counter is refreshed and starts counting operation on  in rzv2h_wdt_ping()
64 	writeb(0x0, priv->base + WDTRR);  in rzv2h_wdt_ping()
65 	writeb(0xFF, priv->base + WDTRR);  in rzv2h_wdt_ping()
75 	writew(wdtcr, priv->base + WDTCR);  in rzv2h_wdt_setup()
77 	/* Enable interrupt output to the ICU. */  in rzv2h_wdt_setup()
78 	writeb(0, priv->base + WDTRCR);  in rzv2h_wdt_setup()
81 	writew(0, priv->base + WDTSR);  in rzv2h_wdt_setup()
89 	ret = pm_runtime_resume_and_get(wdev->parent);  in rzv2h_wdt_start()
93 	ret = reset_control_deassert(priv->rstc);  in rzv2h_wdt_start()
95 		pm_runtime_put(wdev->parent);  in rzv2h_wdt_start()
99 	/* delay to handle clock halt after de-assert operation */  in rzv2h_wdt_start()
104 	 * - CKS[7:4] - Clock Division Ratio Select - 0101b: oscclk/256  in rzv2h_wdt_start()
105 	 * - RPSS[13:12] - Window Start Position Select - 11b: 100%  in rzv2h_wdt_start()
106 	 * - RPES[9:8] - Window End Position Select - 11b: 0%  in rzv2h_wdt_start()
107 	 * - TOPS[1:0] - Timeout Period Select - 11b: 16384 cycles (3FFFh)  in rzv2h_wdt_start()
113 	 * Down counting starts after writing the sequence 00h -> FFh to the  in rzv2h_wdt_start()
126 	ret = reset_control_assert(priv->rstc);  in rzv2h_wdt_stop()
130 	ret = pm_runtime_put(wdev->parent);  in rzv2h_wdt_stop()
139 	.identity = "Renesas RZ/V2H WDT Watchdog",
149 		ret = clk_enable(priv->pclk);  in rzv2h_wdt_restart()
153 		ret = clk_enable(priv->oscclk);  in rzv2h_wdt_restart()
155 			clk_disable(priv->pclk);  in rzv2h_wdt_restart()
159 		ret = reset_control_deassert(priv->rstc);  in rzv2h_wdt_restart()
161 			clk_disable(priv->oscclk);  in rzv2h_wdt_restart()
162 			clk_disable(priv->pclk);  in rzv2h_wdt_restart()
167 		 * Writing to the WDT Control Register (WDTCR) or WDT Reset  in rzv2h_wdt_restart()
168 		 * Control Register (WDTRCR) is possible once between the  in rzv2h_wdt_restart()
172 		ret = reset_control_reset(priv->rstc);  in rzv2h_wdt_restart()
177 	/* delay to handle clock halt after de-assert operation */  in rzv2h_wdt_restart()
182 	 * - CKS[7:4] - Clock Division Ratio Select - 0000b: oscclk/1  in rzv2h_wdt_restart()
183 	 * - RPSS[13:12] - Window Start Position Select - 00b: 25%  in rzv2h_wdt_restart()
184 	 * - RPES[9:8] - Window End Position Select - 00b: 75%  in rzv2h_wdt_restart()
185 	 * - TOPS[1:0] - Timeout Period Select - 00b: 1024 cycles (03FFh)  in rzv2h_wdt_restart()
208 	struct device *dev = &pdev->dev;  in rzv2h_wdt_probe()
214 		return -ENOMEM;  in rzv2h_wdt_probe()
216 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in rzv2h_wdt_probe()
217 	if (IS_ERR(priv->base))  in rzv2h_wdt_probe()
218 		return PTR_ERR(priv->base);  in rzv2h_wdt_probe()
220 	priv->pclk = devm_clk_get_prepared(&pdev->dev, "pclk");  in rzv2h_wdt_probe()
221 	if (IS_ERR(priv->pclk))  in rzv2h_wdt_probe()
222 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");  in rzv2h_wdt_probe()
224 	priv->oscclk = devm_clk_get_prepared(&pdev->dev, "oscclk");  in rzv2h_wdt_probe()
225 	if (IS_ERR(priv->oscclk))  in rzv2h_wdt_probe()
226 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->oscclk), "no oscclk");  in rzv2h_wdt_probe()
228 	priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in rzv2h_wdt_probe()
229 	if (IS_ERR(priv->rstc))  in rzv2h_wdt_probe()
230 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),  in rzv2h_wdt_probe()
233 	priv->wdev.max_hw_heartbeat_ms = (MILLI * MAX_TIMEOUT_CYCLES * CLOCK_DIV_BY_256) /  in rzv2h_wdt_probe()
234 					 clk_get_rate(priv->oscclk);  in rzv2h_wdt_probe()
235 	dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms);  in rzv2h_wdt_probe()
237 	ret = devm_pm_runtime_enable(&pdev->dev);  in rzv2h_wdt_probe()
241 	priv->wdev.min_timeout = 1;  in rzv2h_wdt_probe()
242 	priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;  in rzv2h_wdt_probe()
243 	priv->wdev.info = &rzv2h_wdt_ident;  in rzv2h_wdt_probe()
244 	priv->wdev.ops = &rzv2h_wdt_ops;  in rzv2h_wdt_probe()
245 	priv->wdev.parent = dev;  in rzv2h_wdt_probe()
246 	watchdog_set_drvdata(&priv->wdev, priv);  in rzv2h_wdt_probe()
247 	watchdog_set_nowayout(&priv->wdev, nowayout);  in rzv2h_wdt_probe()
248 	watchdog_stop_on_unregister(&priv->wdev);  in rzv2h_wdt_probe()
250 	ret = watchdog_init_timeout(&priv->wdev, 0, dev);  in rzv2h_wdt_probe()
254 	return devm_watchdog_register_device(&pdev->dev, &priv->wdev);  in rzv2h_wdt_probe()
258 	{ .compatible = "renesas,r9a09g057-wdt", },
271 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
272 MODULE_DESCRIPTION("Renesas RZ/V2H(P) WDT Watchdog Driver");