1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dt-bindings/reset/mt2712-resets.h>
13 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
14 #include <dt-bindings/reset/mt7986-resets.h>
15 #include <dt-bindings/reset/mt8183-resets.h>
16 #include <dt-bindings/reset/mt8186-resets.h>
17 #include <dt-bindings/reset/mt8188-resets.h>
18 #include <dt-bindings/reset/mt8192-resets.h>
19 #include <dt-bindings/reset/mt8195-resets.h>
29 #include <linux/reset-controller.h>
63 #define DRV_NAME		"mtk-wdt"
124  * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
127  * @enable: If true, enable software control for that bit, disable otherwise.
132 					unsigned long id, bool enable)  in toprgu_reset_sw_en_unlocked()  argument
136 	tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);  in toprgu_reset_sw_en_unlocked()
137 	if (enable)  in toprgu_reset_sw_en_unlocked()
142 	writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);  in toprgu_reset_sw_en_unlocked()
153 	spin_lock_irqsave(&data->lock, flags);  in toprgu_reset_update()
155 	if (assert && data->has_swsysrst_en)  in toprgu_reset_update()
158 	tmp = readl(data->wdt_base + WDT_SWSYSRST);  in toprgu_reset_update()
164 	writel(tmp, data->wdt_base + WDT_SWSYSRST);  in toprgu_reset_update()
166 	if (!assert && data->has_swsysrst_en)  in toprgu_reset_update()
169 	spin_unlock_irqrestore(&data->lock, flags);  in toprgu_reset_update()
210 	spin_lock_init(&mtk_wdt->lock);  in toprgu_register_reset_controller()
212 	mtk_wdt->rcdev.owner = THIS_MODULE;  in toprgu_register_reset_controller()
213 	mtk_wdt->rcdev.nr_resets = rst_num;  in toprgu_register_reset_controller()
214 	mtk_wdt->rcdev.ops = &toprgu_reset_ops;  in toprgu_register_reset_controller()
215 	mtk_wdt->rcdev.of_node = pdev->dev.of_node;  in toprgu_register_reset_controller()
216 	ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);  in toprgu_register_reset_controller()
218 		dev_err(&pdev->dev,  in toprgu_register_reset_controller()
219 			"couldn't register wdt reset controller: %d\n", ret);  in toprgu_register_reset_controller()
229 	wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_restart()
242 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_ping()
253 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_set_timeout()
256 	wdt_dev->timeout = timeout;  in mtk_wdt_set_timeout()
261 	if (wdt_dev->pretimeout)  in mtk_wdt_set_timeout()
262 		wdt_dev->pretimeout = timeout / 2;  in mtk_wdt_set_timeout()
268 	reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)  in mtk_wdt_set_timeout()
282 	wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_init()
285 		set_bit(WDOG_HW_RUNNING, &wdt_dev->status);  in mtk_wdt_init()
286 		mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);  in mtk_wdt_init()
293 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_stop()
308 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_start()
311 	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);  in mtk_wdt_start()
316 	if (wdt_dev->pretimeout)  in mtk_wdt_start()
320 	if (mtk_wdt->disable_wdt_extrst)  in mtk_wdt_start()
322 	if (mtk_wdt->reset_by_toprgu)  in mtk_wdt_start()
334 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_set_pretimeout()
337 	if (timeout && !wdd->pretimeout) {  in mtk_wdt_set_pretimeout()
338 		wdd->pretimeout = wdd->timeout / 2;  in mtk_wdt_set_pretimeout()
340 	} else if (!timeout && wdd->pretimeout) {  in mtk_wdt_set_pretimeout()
341 		wdd->pretimeout = 0;  in mtk_wdt_set_pretimeout()
350 	return mtk_wdt_set_timeout(wdd, wdd->timeout);  in mtk_wdt_set_pretimeout()
389 	struct device *dev = &pdev->dev;  in mtk_wdt_probe()
396 		return -ENOMEM;  in mtk_wdt_probe()
400 	mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);  in mtk_wdt_probe()
401 	if (IS_ERR(mtk_wdt->wdt_base))  in mtk_wdt_probe()
402 		return PTR_ERR(mtk_wdt->wdt_base);  in mtk_wdt_probe()
406 		err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",  in mtk_wdt_probe()
407 				       &mtk_wdt->wdt_dev);  in mtk_wdt_probe()
411 		mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;  in mtk_wdt_probe()
412 		mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;  in mtk_wdt_probe()
414 		if (irq == -EPROBE_DEFER)  in mtk_wdt_probe()
415 			return -EPROBE_DEFER;  in mtk_wdt_probe()
417 		mtk_wdt->wdt_dev.info = &mtk_wdt_info;  in mtk_wdt_probe()
420 	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;  in mtk_wdt_probe()
421 	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;  in mtk_wdt_probe()
422 	mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;  in mtk_wdt_probe()
423 	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;  in mtk_wdt_probe()
424 	mtk_wdt->wdt_dev.parent = dev;  in mtk_wdt_probe()
426 	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);  in mtk_wdt_probe()
427 	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);  in mtk_wdt_probe()
428 	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);  in mtk_wdt_probe()
430 	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);  in mtk_wdt_probe()
432 	mtk_wdt_init(&mtk_wdt->wdt_dev);  in mtk_wdt_probe()
434 	watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);  in mtk_wdt_probe()
435 	err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);  in mtk_wdt_probe()
440 		 mtk_wdt->wdt_dev.timeout, nowayout);  in mtk_wdt_probe()
445 						       wdt_data->toprgu_sw_rst_num);  in mtk_wdt_probe()
449 		mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;  in mtk_wdt_probe()
452 	mtk_wdt->disable_wdt_extrst =  in mtk_wdt_probe()
453 		of_property_read_bool(dev->of_node, "mediatek,disable-extrst");  in mtk_wdt_probe()
455 	mtk_wdt->reset_by_toprgu =  in mtk_wdt_probe()
456 		of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");  in mtk_wdt_probe()
465 	if (watchdog_active(&mtk_wdt->wdt_dev))  in mtk_wdt_suspend()
466 		mtk_wdt_stop(&mtk_wdt->wdt_dev);  in mtk_wdt_suspend()
475 	if (watchdog_active(&mtk_wdt->wdt_dev)) {  in mtk_wdt_resume()
476 		mtk_wdt_start(&mtk_wdt->wdt_dev);  in mtk_wdt_resume()
477 		mtk_wdt_ping(&mtk_wdt->wdt_dev);  in mtk_wdt_resume()
484 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
485 	{ .compatible = "mediatek,mt6589-wdt" },
486 	{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
487 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
488 	{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
489 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
490 	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
491 	{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
492 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
493 	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
516 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="