1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dt-bindings/reset/mt2712-resets.h>
13 #include <dt-bindings/reset/mediatek,mt6735-wdt.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
15 #include <dt-bindings/reset/mt7986-resets.h>
16 #include <dt-bindings/reset/mt8183-resets.h>
17 #include <dt-bindings/reset/mt8186-resets.h>
18 #include <dt-bindings/reset/mt8188-resets.h>
19 #include <dt-bindings/reset/mt8192-resets.h>
20 #include <dt-bindings/reset/mt8195-resets.h>
30 #include <linux/reset-controller.h>
64 #define DRV_NAME		"mtk-wdt"
129  * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
141 	tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);  in toprgu_reset_sw_en_unlocked()
147 	writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);  in toprgu_reset_sw_en_unlocked()
158 	spin_lock_irqsave(&data->lock, flags);  in toprgu_reset_update()
160 	if (assert && data->has_swsysrst_en)  in toprgu_reset_update()
163 	tmp = readl(data->wdt_base + WDT_SWSYSRST);  in toprgu_reset_update()
169 	writel(tmp, data->wdt_base + WDT_SWSYSRST);  in toprgu_reset_update()
171 	if (!assert && data->has_swsysrst_en)  in toprgu_reset_update()
174 	spin_unlock_irqrestore(&data->lock, flags);  in toprgu_reset_update()
215 	spin_lock_init(&mtk_wdt->lock);  in toprgu_register_reset_controller()
217 	mtk_wdt->rcdev.owner = THIS_MODULE;  in toprgu_register_reset_controller()
218 	mtk_wdt->rcdev.nr_resets = rst_num;  in toprgu_register_reset_controller()
219 	mtk_wdt->rcdev.ops = &toprgu_reset_ops;  in toprgu_register_reset_controller()
220 	mtk_wdt->rcdev.of_node = pdev->dev.of_node;  in toprgu_register_reset_controller()
221 	ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);  in toprgu_register_reset_controller()
223 		dev_err(&pdev->dev,  in toprgu_register_reset_controller()
224 			"couldn't register wdt reset controller: %d\n", ret);  in toprgu_register_reset_controller()
235 	wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_restart()
253 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_ping()
264 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_set_timeout()
267 	wdt_dev->timeout = timeout;  in mtk_wdt_set_timeout()
272 	if (wdt_dev->pretimeout)  in mtk_wdt_set_timeout()
273 		wdt_dev->pretimeout = timeout / 2;  in mtk_wdt_set_timeout()
279 	reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)  in mtk_wdt_set_timeout()
293 	wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_init()
296 		set_bit(WDOG_HW_RUNNING, &wdt_dev->status);  in mtk_wdt_init()
297 		mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);  in mtk_wdt_init()
304 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_stop()
319 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_start()
322 	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);  in mtk_wdt_start()
327 	if (wdt_dev->pretimeout)  in mtk_wdt_start()
331 	if (mtk_wdt->disable_wdt_extrst)  in mtk_wdt_start()
333 	if (mtk_wdt->reset_by_toprgu)  in mtk_wdt_start()
345 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_set_pretimeout()
348 	if (timeout && !wdd->pretimeout) {  in mtk_wdt_set_pretimeout()
349 		wdd->pretimeout = wdd->timeout / 2;  in mtk_wdt_set_pretimeout()
351 	} else if (!timeout && wdd->pretimeout) {  in mtk_wdt_set_pretimeout()
352 		wdd->pretimeout = 0;  in mtk_wdt_set_pretimeout()
361 	return mtk_wdt_set_timeout(wdd, wdd->timeout);  in mtk_wdt_set_pretimeout()
400 	struct device *dev = &pdev->dev;  in mtk_wdt_probe()
407 		return -ENOMEM;  in mtk_wdt_probe()
411 	mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);  in mtk_wdt_probe()
412 	if (IS_ERR(mtk_wdt->wdt_base))  in mtk_wdt_probe()
413 		return PTR_ERR(mtk_wdt->wdt_base);  in mtk_wdt_probe()
417 		err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",  in mtk_wdt_probe()
418 				       &mtk_wdt->wdt_dev);  in mtk_wdt_probe()
422 		mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;  in mtk_wdt_probe()
423 		mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;  in mtk_wdt_probe()
425 		if (irq == -EPROBE_DEFER)  in mtk_wdt_probe()
426 			return -EPROBE_DEFER;  in mtk_wdt_probe()
428 		mtk_wdt->wdt_dev.info = &mtk_wdt_info;  in mtk_wdt_probe()
431 	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;  in mtk_wdt_probe()
432 	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;  in mtk_wdt_probe()
433 	mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;  in mtk_wdt_probe()
434 	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;  in mtk_wdt_probe()
435 	mtk_wdt->wdt_dev.parent = dev;  in mtk_wdt_probe()
437 	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);  in mtk_wdt_probe()
438 	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);  in mtk_wdt_probe()
439 	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);  in mtk_wdt_probe()
441 	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);  in mtk_wdt_probe()
443 	mtk_wdt_init(&mtk_wdt->wdt_dev);  in mtk_wdt_probe()
445 	watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);  in mtk_wdt_probe()
446 	err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);  in mtk_wdt_probe()
451 		 mtk_wdt->wdt_dev.timeout, nowayout);  in mtk_wdt_probe()
456 						       wdt_data->toprgu_sw_rst_num);  in mtk_wdt_probe()
460 		mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;  in mtk_wdt_probe()
463 	mtk_wdt->disable_wdt_extrst =  in mtk_wdt_probe()
464 		of_property_read_bool(dev->of_node, "mediatek,disable-extrst");  in mtk_wdt_probe()
466 	mtk_wdt->reset_by_toprgu =  in mtk_wdt_probe()
467 		of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");  in mtk_wdt_probe()
476 	if (watchdog_active(&mtk_wdt->wdt_dev))  in mtk_wdt_suspend()
477 		mtk_wdt_stop(&mtk_wdt->wdt_dev);  in mtk_wdt_suspend()
486 	if (watchdog_active(&mtk_wdt->wdt_dev)) {  in mtk_wdt_resume()
487 		mtk_wdt_start(&mtk_wdt->wdt_dev);  in mtk_wdt_resume()
488 		mtk_wdt_ping(&mtk_wdt->wdt_dev);  in mtk_wdt_resume()
495 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
496 	{ .compatible = "mediatek,mt6589-wdt" },
497 	{ .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data },
498 	{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
499 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
500 	{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
501 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
502 	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
503 	{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
504 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
505 	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },