59  *    0x180, 0x280, 0x380 with an additional offset of 0xc10.
60  *    (Or 0xd90, 0xe90, 0xf90).
62  *    0x300 -> 0x378, in 0x8 jumps with an offset of 0x04.
63  *    (Or 0x304 -> 0x37c in 0x8 jumps).
66 #define MIXCOM_ID 0x11
67 #define FLASHCOM_ID 0x18
73 	{0x0d90, MIXCOM_ID},
74 	{0x0e90, MIXCOM_ID},
75 	{0x0f90, MIXCOM_ID},
77 	{0x0304, FLASHCOM_ID},
78 	{0x030c, FLASHCOM_ID},
79 	{0x0314, FLASHCOM_ID},
80 	{0x031c, FLASHCOM_ID},
81 	{0x0324, FLASHCOM_ID},
82 	{0x032c, FLASHCOM_ID},
83 	{0x0334, FLASHCOM_ID},
84 	{0x033c, FLASHCOM_ID},
85 	{0x0344, FLASHCOM_ID},
86 	{0x034c, FLASHCOM_ID},
87 	{0x0354, FLASHCOM_ID},
88 	{0x035c, FLASHCOM_ID},
89 	{0x0364, FLASHCOM_ID},
90 	{0x036c, FLASHCOM_ID},
91 	{0x0374, FLASHCOM_ID},
92 	{0x037c, FLASHCOM_ID},
94 	{0x0000, 0},
107 module_param(nowayout, bool, 0);
130 	if (test_and_set_bit(0, &mixcomwd_opened))  in mixcomwd_open()
145 			mixcomwd_timer_alive = 0;  in mixcomwd_open()
163 	clear_bit(0, &mixcomwd_opened);  in mixcomwd_release()
164 	expect_close = 0;  in mixcomwd_release()
165 	return 0;  in mixcomwd_release()
177 			expect_close = 0;  in mixcomwd_write()
179 			for (i = 0; i != len; i++) {  in mixcomwd_write()
215 		return put_user(0, p);  in mixcomwd_ioctl()
222 	return 0;  in mixcomwd_ioctl()
245 		return 0;  in checkcard()
249 		id &= 0x3f;  in checkcard()
253 		return 0;  in checkcard()
260 	int i, ret, found = 0;  in mixcomwd_init()
262 	for (i = 0; !found && mixcomwd_io_info[i].ioport != 0; i++) {  in mixcomwd_init()
282 	pr_info("MixCOM watchdog driver v%s, watchdog port at 0x%3x\n",  in mixcomwd_init()
285 	return 0;  in mixcomwd_init()
289 	watchdog_port = 0x0000;  in mixcomwd_init()
299 			mixcomwd_timer_alive = 0;  in mixcomwd_exit()