Lines Matching +full:duration +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0-or-later
57 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
58 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
59 { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
89 * * Pulse duration
90 * * Drive mode: push-pull vs open-drain
93 * Pulse duration configuration is available on both the AST2400 and AST2500,
103 * and bit 30 represents push-pull or open-drain. With respect to write, magic
131 wdt->ctrl |= WDT_CTRL_ENABLE; in aspeed_wdt_enable()
133 writel(0, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
134 writel(count, wdt->base + WDT_RELOAD_VALUE); in aspeed_wdt_enable()
135 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_enable()
136 writel(wdt->ctrl, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
143 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ); in aspeed_wdt_start()
152 wdt->ctrl &= ~WDT_CTRL_ENABLE; in aspeed_wdt_stop()
153 writel(wdt->ctrl, wdt->base + WDT_CTRL); in aspeed_wdt_stop()
162 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_ping()
173 wdd->timeout = timeout; in aspeed_wdt_set_timeout()
175 actual = min(timeout, wdd->max_hw_heartbeat_ms / 1000); in aspeed_wdt_set_timeout()
177 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE); in aspeed_wdt_set_timeout()
178 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_set_timeout()
188 u32 s = wdt->cfg->irq_shift; in aspeed_wdt_set_pretimeout()
189 u32 m = wdt->cfg->irq_mask; in aspeed_wdt_set_pretimeout()
191 wdd->pretimeout = pretimeout; in aspeed_wdt_set_pretimeout()
192 wdt->ctrl &= ~m; in aspeed_wdt_set_pretimeout()
194 wdt->ctrl |= ((actual << s) & m) | WDT_CTRL_WDT_INTR; in aspeed_wdt_set_pretimeout()
196 wdt->ctrl &= ~WDT_CTRL_WDT_INTR; in aspeed_wdt_set_pretimeout()
198 writel(wdt->ctrl, wdt->base + WDT_CTRL); in aspeed_wdt_set_pretimeout()
208 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY; in aspeed_wdt_restart()
221 u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS); in access_cs0_show()
235 return -EINVAL; in access_cs0_store()
239 wdt->base + WDT_CLEAR_TIMEOUT_STATUS); in access_cs0_store()
246 * flash with 'alt-boot' option.
252 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
299 u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS); in aspeed_wdt_irq()
309 struct device *dev = &pdev->dev; in aspeed_wdt_probe()
314 u32 duration; in aspeed_wdt_probe() local
320 return -ENOMEM; in aspeed_wdt_probe()
322 np = dev->of_node; in aspeed_wdt_probe()
326 return -EINVAL; in aspeed_wdt_probe()
327 wdt->cfg = ofdid->data; in aspeed_wdt_probe()
329 wdt->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_wdt_probe()
330 if (IS_ERR(wdt->base)) in aspeed_wdt_probe()
331 return PTR_ERR(wdt->base); in aspeed_wdt_probe()
333 wdt->wdd.info = &aspeed_wdt_info; in aspeed_wdt_probe()
335 if (wdt->cfg->irq_mask) { in aspeed_wdt_probe()
345 wdt->wdd.info = &aspeed_wdt_pretimeout_info; in aspeed_wdt_probe()
349 wdt->wdd.ops = &aspeed_wdt_ops; in aspeed_wdt_probe()
350 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS; in aspeed_wdt_probe()
351 wdt->wdd.parent = dev; in aspeed_wdt_probe()
353 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; in aspeed_wdt_probe()
354 watchdog_init_timeout(&wdt->wdd, 0, dev); in aspeed_wdt_probe()
356 watchdog_set_nowayout(&wdt->wdd, nowayout); in aspeed_wdt_probe()
360 * - ast2400 wdt can run at PCLK, or 1MHz in aspeed_wdt_probe()
361 * - ast2500 only runs at 1MHz, hard coding bit 4 to 1 in aspeed_wdt_probe()
362 * - ast2600 always runs at 1MHz in aspeed_wdt_probe()
366 if (of_device_is_compatible(np, "aspeed,ast2400-wdt")) in aspeed_wdt_probe()
367 wdt->ctrl = WDT_CTRL_1MHZ_CLK; in aspeed_wdt_probe()
370 * Control reset on a per-device basis to ensure the in aspeed_wdt_probe()
373 ret = of_property_read_string(np, "aspeed,reset-type", &reset_type); in aspeed_wdt_probe()
375 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; in aspeed_wdt_probe()
378 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU | in aspeed_wdt_probe()
381 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | in aspeed_wdt_probe()
384 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP | in aspeed_wdt_probe()
387 return -EINVAL; in aspeed_wdt_probe()
389 if (of_property_read_bool(np, "aspeed,external-signal")) in aspeed_wdt_probe()
390 wdt->ctrl |= WDT_CTRL_WDT_EXT; in aspeed_wdt_probe()
391 if (of_property_read_bool(np, "aspeed,alt-boot")) in aspeed_wdt_probe()
392 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY; in aspeed_wdt_probe()
394 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { in aspeed_wdt_probe()
397 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's in aspeed_wdt_probe()
401 aspeed_wdt_start(&wdt->wdd); in aspeed_wdt_probe()
402 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); in aspeed_wdt_probe()
405 if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) || in aspeed_wdt_probe()
406 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) { in aspeed_wdt_probe()
408 size_t nrstmask = of_device_is_compatible(np, "aspeed,ast2600-wdt") ? 2 : 1; in aspeed_wdt_probe()
409 u32 reg = readl(wdt->base + WDT_RESET_WIDTH); in aspeed_wdt_probe()
411 reg &= wdt->cfg->ext_pulse_width_mask; in aspeed_wdt_probe()
412 if (of_property_read_bool(np, "aspeed,ext-active-high")) in aspeed_wdt_probe()
417 writel(reg, wdt->base + WDT_RESET_WIDTH); in aspeed_wdt_probe()
419 reg &= wdt->cfg->ext_pulse_width_mask; in aspeed_wdt_probe()
420 if (of_property_read_bool(np, "aspeed,ext-push-pull")) in aspeed_wdt_probe()
425 writel(reg, wdt->base + WDT_RESET_WIDTH); in aspeed_wdt_probe()
427 ret = of_property_read_u32_array(np, "aspeed,reset-mask", reset_mask, nrstmask); in aspeed_wdt_probe()
429 writel(reset_mask[0], wdt->base + WDT_RESET_MASK1); in aspeed_wdt_probe()
431 writel(reset_mask[1], wdt->base + WDT_RESET_MASK2); in aspeed_wdt_probe()
435 if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) { in aspeed_wdt_probe()
436 u32 max_duration = wdt->cfg->ext_pulse_width_mask + 1; in aspeed_wdt_probe()
438 if (duration == 0 || duration > max_duration) { in aspeed_wdt_probe()
439 dev_err(dev, "Invalid pulse duration: %uus\n", in aspeed_wdt_probe()
440 duration); in aspeed_wdt_probe()
441 duration = max(1U, min(max_duration, duration)); in aspeed_wdt_probe()
442 dev_info(dev, "Pulse duration set to %uus\n", in aspeed_wdt_probe()
443 duration); in aspeed_wdt_probe()
449 * need to offset it - from the datasheet: in aspeed_wdt_probe()
451 * "This register decides the asserting duration of wdt_ext and in aspeed_wdt_probe()
453 * default asserting duration of wdt_ext and wdt_rstarm is in aspeed_wdt_probe()
454 * 256us." in aspeed_wdt_probe()
456 * This implies a value of 0 gives a 1us pulse. in aspeed_wdt_probe()
458 writel(duration - 1, wdt->base + WDT_RESET_WIDTH); in aspeed_wdt_probe()
461 status = readl(wdt->base + WDT_TIMEOUT_STATUS); in aspeed_wdt_probe()
463 wdt->wdd.bootstatus = WDIOF_CARDRESET; in aspeed_wdt_probe()
465 if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || in aspeed_wdt_probe()
466 of_device_is_compatible(np, "aspeed,ast2500-wdt")) in aspeed_wdt_probe()
467 wdt->wdd.groups = bswitch_groups; in aspeed_wdt_probe()
472 return devm_watchdog_register_device(dev, &wdt->wdd); in aspeed_wdt_probe()