Lines Matching full:wire
3 * w1-uart - UART 1-Wire bus driver
5 * Uses the UART interface (via Serial Device Bus) to create the 1-Wire
6 * timing patterns. Implements the following 1-Wire master interface:
31 * struct w1_uart_config - configuration for 1-Wire operation
33 * @delay_us: delay to complete a 1-Wire cycle (in us)
34 * @tx_byte: byte to generate 1-Wire timing pattern
43 * struct w1_uart_device - 1-Wire UART device structure
46 * @cfg_reset: config for 1-Wire reset
47 * @cfg_touch_0: config for 1-Wire write-0 cycle
48 * @cfg_touch_1: config for 1-Wire write-1 and read cycle
73 * struct w1_uart_limits - limits for 1-Wire operations
74 * @baudrate: Requested baud-rate to create 1-Wire timing pattern
77 * @sample_us: timespan to sample 1-Wire response
78 * @cycle_us: duration of the 1-Wire cycle
99 * Set baud-rate, delay and tx-byte to create a 1-Wire pulse and adapt
104 * - a 1-Wire response is not detectable for sent byte
131 /* 1-Wire response detectable for sent byte */ in w1_uart_set_config()
136 /* delay: 1-Wire cycle takes longer than the UART packet */ in w1_uart_set_config()
143 /* byte to create 1-Wire pulse */ in w1_uart_set_config()
319 * 1-wire reset and presence detect: A present slave will manipulate
320 * the received byte by pulling the 1-Wire low.
338 * 1-Wire read and write cycle: Only the read-0 manipulates the