Lines Matching refs:AXIW1_STAT_REG
29 #define AXIW1_STAT_REG 0xC macro
114 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_touch_bit()
133 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_touch_bit()
162 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_read_byte()
176 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_read_byte()
203 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_write_byte()
217 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_write_byte()
244 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_reset_bus()
257 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_reset_bus()
263 if ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_PRESENCE) != 0) in amd_axi_w1_reset_bus()
278 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_STAT_REG); in amd_axi_w1_reset()