Lines Matching +full:0 +full:x0e
13 {19, 19, 4, 0},
14 {26, 102, 5, 0},
15 {53, 112, 6, 0},
16 {41, 100, 7, 0},
17 {83, 108, 8, 0},
18 {87, 118, 9, 0},
19 {95, 115, 12, 0},
20 {108, 108, 13, 0},
21 {83, 83, 17, 0},
22 {67, 98, 20, 0},
23 {121, 121, 24, 0},
24 {99, 99, 29, 0},
44 {22, 22, 2, 0},
45 {28, 28, 3, 0},
90 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
91 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
92 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
93 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
94 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
95 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
96 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
97 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
98 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
99 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
100 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
101 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
102 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
103 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
107 {VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8)
115 {VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan
117 {VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line
121 {VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start
123 {VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end
125 {VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */
126 {VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */
127 {VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end
130 {VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location
133 {VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14
139 {VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */
144 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
152 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
154 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
159 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
161 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
166 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
168 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
174 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
176 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
181 /* Index 0x00~0x03 */
182 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
183 0x2A,
184 0x2A},
185 /* Index 0x04~0x07 */
186 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
187 0x2A,
188 0x2A},
189 /* Index 0x08~0x0B */
190 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
191 0x3F,
192 0x3F},
193 /* Index 0x0C~0x0F */
194 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
195 0x3F,
196 0x3F},
197 /* Index 0x10~0x13 */
198 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
199 0x0B,
200 0x0B},
201 /* Index 0x14~0x17 */
202 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
203 0x18,
204 0x18},
205 /* Index 0x18~0x1B */
206 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
207 0x28,
208 0x28},
209 /* Index 0x1C~0x1F */
210 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
211 0x3F,
212 0x3F},
213 /* Index 0x20~0x23 */
214 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
215 0x00,
216 0x3F},
217 /* Index 0x24~0x27 */
218 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
219 0x00,
220 0x10},
221 /* Index 0x28~0x2B */
222 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
223 0x2F,
224 0x00},
225 /* Index 0x2C~0x2F */
226 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
227 0x3F,
228 0x00},
229 /* Index 0x30~0x33 */
230 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
231 0x3F,
232 0x2F},
233 /* Index 0x34~0x37 */
234 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
235 0x10,
236 0x3F},
237 /* Index 0x38~0x3B */
238 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
239 0x1F,
240 0x3F},
241 /* Index 0x3C~0x3F */
242 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
243 0x1F,
244 0x27},
245 /* Index 0x40~0x43 */
246 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
247 0x3F,
248 0x1F},
249 /* Index 0x44~0x47 */
250 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
251 0x3F,
252 0x1F},
253 /* Index 0x48~0x4B */
254 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
255 0x3F,
256 0x37},
257 /* Index 0x4C~0x4F */
258 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
259 0x27,
260 0x3F},
261 /* Index 0x50~0x53 */
262 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
263 0x2D,
264 0x3F},
265 /* Index 0x54~0x57 */
266 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
267 0x2D,
268 0x31},
269 /* Index 0x58~0x5B */
270 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
271 0x3A,
272 0x2D},
273 /* Index 0x5C~0x5F */
274 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
275 0x3F,
276 0x2D},
277 /* Index 0x60~0x63 */
278 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
279 0x3F,
280 0x3A},
281 /* Index 0x64~0x67 */
282 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
283 0x31,
284 0x3F},
285 /* Index 0x68~0x6B */
286 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
287 0x00,
288 0x1C},
289 /* Index 0x6C~0x6F */
290 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
291 0x00,
292 0x07},
293 /* Index 0x70~0x73 */
294 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
295 0x15,
296 0x00},
297 /* Index 0x74~0x77 */
298 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
299 0x1C,
300 0x00},
301 /* Index 0x78~0x7B */
302 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
303 0x1C,
304 0x15},
305 /* Index 0x7C~0x7F */
306 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
307 0x07,
308 0x1C},
309 /* Index 0x80~0x83 */
310 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
311 0x0E,
312 0x1C},
313 /* Index 0x84~0x87 */
314 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
315 0x0E,
316 0x11},
317 /* Index 0x88~0x8B */
318 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
319 0x18,
320 0x0E},
321 /* Index 0x8C~0x8F */
322 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
323 0x1C,
324 0x0E},
325 /* Index 0x90~0x93 */
326 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
327 0x1C,
328 0x18},
329 /* Index 0x94~0x97 */
330 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
331 0x11,
332 0x1C},
333 /* Index 0x98~0x9B */
334 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
335 0x14,
336 0x1C},
337 /* Index 0x9C~0x9F */
338 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
339 0x14,
340 0x16},
341 /* Index 0xA0~0xA3 */
342 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
343 0x1A,
344 0x14},
345 /* Index 0xA4~0xA7 */
346 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
347 0x1C,
348 0x14},
349 /* Index 0xA8~0xAB */
350 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
351 0x1C,
352 0x1A},
353 /* Index 0xAC~0xAF */
354 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
355 0x16,
356 0x1C},
357 /* Index 0xB0~0xB3 */
358 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
359 0x00,
360 0x10},
361 /* Index 0xB4~0xB7 */
362 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
363 0x00,
364 0x04},
365 /* Index 0xB8~0xBB */
366 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
367 0x0C,
368 0x00},
369 /* Index 0xBC~0xBF */
370 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
371 0x10,
372 0x00},
373 /* Index 0xC0~0xC3 */
374 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
375 0x10,
376 0x0C},
377 /* Index 0xC4~0xC7 */
378 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
379 0x04,
380 0x10},
381 /* Index 0xC8~0xCB */
382 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
383 0x08,
384 0x10},
385 /* Index 0xCC~0xCF */
386 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
387 0x08,
388 0x0A},
389 /* Index 0xD0~0xD3 */
390 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
391 0x0E,
392 0x08},
393 /* Index 0xD4~0xD7 */
394 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
395 0x10,
396 0x08},
397 /* Index 0xD8~0xDB */
398 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
399 0x10,
400 0x0E},
401 /* Index 0xDC~0xDF */
402 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
403 0x0A,
404 0x10},
405 /* Index 0xE0~0xE3 */
406 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
407 0x0B,
408 0x10},
409 /* Index 0xE4~0xE7 */
410 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
411 0x0B,
412 0x0C},
413 /* Index 0xE8~0xEB */
414 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
415 0x0F,
416 0x0B},
417 /* Index 0xEC~0xEF */
418 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
419 0x10,
420 0x0B},
421 /* Index 0xF0~0xF3 */
422 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
423 0x10,
424 0x0F},
425 /* Index 0xF4~0xF7 */
426 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
427 0x0C,
428 0x10},
429 /* Index 0xF8~0xFB */
430 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
431 0x00,
432 0x00},
433 /* Index 0xFC~0xFF */
434 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
435 0x00,
436 0x00}
471 viafb_write_reg_mask(CR11, VIACR, 0, BIT7); in viafb_unlock_crt()
472 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
497 return 0; in get_dvi_devices()
503 return 0; in get_dvi_devices()
511 return 0; in get_dvi_devices()
540 return 0; in get_lcd_devices()
546 int crt_iga_path = 0; in viafb_set_iga_path()
587 viafb_SAMM_ON = 0; in viafb_set_iga_path()
610 viaparinfo->shared->iga1_devices = 0; in viafb_set_iga_path()
611 viaparinfo->shared->iga2_devices = 0; in viafb_set_iga_path()
659 outb(0xFF, 0x3C6); /* bit mask of palette */ in set_color_register()
660 outb(index, 0x3C8); in set_color_register()
661 outb(red, 0x3C9); in set_color_register()
662 outb(green, 0x3C9); in set_color_register()
663 outb(blue, 0x3C9); in set_color_register()
668 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); in viafb_set_primary_color_register()
674 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); in viafb_set_secondary_color_register()
684 value = 0x00; in set_source_common()
703 value = 0x00; in set_crt_source()
706 value = 0x40; in set_crt_source()
713 via_write_reg_mask(VIASR, 0x16, value, 0x40); in set_crt_source()
718 set_source_common(0x6C, 7, iga); in set_ldvp0_source()
723 set_source_common(0x93, 7, iga); in set_ldvp1_source()
728 set_source_common(0x96, 4, iga); in set_dvp0_source()
733 set_source_common(0x9B, 4, iga); in set_dvp1_source()
738 set_source_common(0x99, 4, iga); in set_lvds1_source()
743 set_source_common(0x97, 4, iga); in set_lvds2_source()
770 value = 0x00; in set_crt_state()
773 value = 0x10; in set_crt_state()
776 value = 0x20; in set_crt_state()
779 value = 0x30; in set_crt_state()
785 via_write_reg_mask(VIACR, 0x36, value, 0x30); in set_crt_state()
794 value = 0xC0; in set_dvp0_state()
797 value = 0x00; in set_dvp0_state()
803 via_write_reg_mask(VIASR, 0x1E, value, 0xC0); in set_dvp0_state()
812 value = 0x30; in set_dvp1_state()
815 value = 0x00; in set_dvp1_state()
821 via_write_reg_mask(VIASR, 0x1E, value, 0x30); in set_dvp1_state()
830 value = 0x03; in set_lvds1_state()
833 value = 0x00; in set_lvds1_state()
839 via_write_reg_mask(VIASR, 0x2A, value, 0x03); in set_lvds1_state()
848 value = 0x0C; in set_lvds2_state()
851 value = 0x00; in set_lvds2_state()
857 via_write_reg_mask(VIASR, 0x2A, value, 0x0C); in set_lvds2_state()
888 via_write_misc_reg_mask(polarity << 6, 0xC0); in via_set_sync_polarity()
890 via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60); in via_set_sync_polarity()
892 via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60); in via_set_sync_polarity()
894 via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60); in via_set_sync_polarity()
900 u32 odev = 0; in via_parse_odev()
906 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { in via_parse_odev()
925 int i, count = 0; in via_odev_to_seq()
927 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { in via_odev_to_seq()
929 if (count > 0) in via_odev_to_seq()
945 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); in load_fix_bit_crtc_reg()
947 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); in load_fix_bit_crtc_reg()
949 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
950 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */ in load_fix_bit_crtc_reg()
957 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3); in load_fix_bit_crtc_reg()
960 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); in load_fix_bit_crtc_reg()
969 int bit_num = 0; in viafb_load_reg()
976 for (i = 0; i < viafb_load_reg_num; i++) { in viafb_load_reg()
977 reg_mask = 0; in viafb_load_reg()
978 data = 0; in viafb_load_reg()
1007 for (i = 0; i < ItemNum; i++) in viafb_write_regx()
1042 int iga1_fifo_max_depth = 0, iga1_fifo_threshold = in viafb_load_FIFO_reg()
1043 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0; in viafb_load_FIFO_reg()
1044 int iga2_fifo_max_depth = 0, iga2_fifo_threshold = in viafb_load_FIFO_reg()
1045 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0; in viafb_load_FIFO_reg()
1376 struct via_pll_config cur, up, down, best = {0, 1, 0}; in get_pll_config()
1380 for (i = 0; i < size; i++) { in get_pll_config()
1452 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ in viafb_set_vclock()
1515 if (flag == 0) { in viafb_update_device_setting()
1538 viafb_write_reg(CR4F, VIACR, 0x55); in init_gfx_chip_info()
1539 if (viafb_read_reg(VIACR, CR4F) != 0x55) in init_gfx_chip_info()
1552 if (tmp & 0x02) { in init_gfx_chip_info()
1555 } else if (tmp & 0x40) { in init_gfx_chip_info()
1667 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1669 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1670 for (i = 0; i < 256; i++) { in viafb_init_dac()
1676 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1680 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
1681 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_init_dac()
1682 for (i = 0; i < 256; i++) { in viafb_init_dac()
1688 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1696 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1702 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1713 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1717 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1720 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1725 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
1735 u8 polarity = 0; in get_sync()
1749 outb(0x00, VIAAR); in hw_init()
1786 via_write_reg_mask(VIACR, 0x45, 0x00, 0x01); in hw_init()
1789 via_write_reg_mask(VIACR, 0xFD, 0, 0x80); /* VX900 hw scale on IGA2 */ in hw_init()
1800 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2); in hw_init()
1803 for (i = 0; i < StdGR; i++) in hw_init()
1807 for (i = 0; i < StdAR; i++) { in hw_init()
1814 outb(0x20, VIAAR); in hw_init()
1821 int j, cxres = 0, cyres = 0; in viafb_setmode()
1839 for (j = 0; j < res_patch_table[0].table_length; j++) { in viafb_setmode()
1840 index = res_patch_table[0].io_reg_table[j].index; in viafb_setmode()
1841 port = res_patch_table[0].io_reg_table[j].port; in viafb_setmode()
1842 value = res_patch_table[0].io_reg_table[j].value; in viafb_setmode()
1843 mask = res_patch_table[0].io_reg_table[j].mask; in viafb_setmode()
1881 viafb_fill_crtc_timing(&viafbinfo->var, 0, 0, in viafb_setmode()
1901 viafb_dvi_set_mode(&viafbinfo->var, 0, 0, in viafb_setmode()
1917 viafb_lcd_set_mode(&viafbinfo->var, 0, 0, in viafb_setmode()
1934 viafb_lcd_set_mode(&viafbinfo->var, 0, 0, in viafb_setmode()
2033 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2041 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2042 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); in disable_second_display_channel()
2054 p_gfx_dpa_setting->DVP0, 0x0F); in viafb_set_dpa_gfx()
2073 p_gfx_dpa_setting->DVP1, 0x0F); in viafb_set_dpa_gfx()
2077 p_gfx_dpa_setting->DVP1Driving, 0x0F); in viafb_set_dpa_gfx()
2084 p_gfx_dpa_setting->DFPHigh, 0x0F); in viafb_set_dpa_gfx()
2091 p_gfx_dpa_setting->DFPLow, 0x0F); in viafb_set_dpa_gfx()
2098 p_gfx_dpa_setting->DFPHigh, 0x0F); in viafb_set_dpa_gfx()
2100 p_gfx_dpa_setting->DFPLow, 0x0F); in viafb_set_dpa_gfx()