165 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)  in t_outb()  function
400 	t_outb(par, x, 0x2125);  in xp_init_accel()
406 	t_outb(par, 3, 0x2126);  in xp_init_accel()
422 				t_outb(par, 0x00, STATUS);  in xp_wait_engine()
438 	t_outb(par, 0x01, OLDCMD);  in xp_fill_rect()
439 	t_outb(par, par->eng_oper, 0x2125);  in xp_fill_rect()
467 	t_outb(par, ROP_S, 0x2127);  in xp_copy_rect()
471 	t_outb(par, 0x01, OLDCMD);  in xp_copy_rect()
573 	t_outb(par, ROP_P, 0x2127);  in tgui_fill_rect()
578 	t_outb(par, 1, OLDCMD);  in tgui_fill_rect()
606 	t_outb(par, ROP_S, 0x2127);  in tgui_copy_rect()
610 	t_outb(par, 1, OLDCMD);  in tgui_copy_rect()
751 	t_outb(par, PCIReg, 0x3D4);  in disable_mmio()
752 	t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);  in disable_mmio()
874 		t_outb(par, lo, 0x43C8);  in set_vclk()
875 		t_outb(par, hi, 0x43C9);  in set_vclk()
1181 		t_outb(par, tmp | 0xC0, VGA_MIS_W);  in tridentfb_set_par()
1191 		t_outb(par, tmp, VGA_MIS_W);  in tridentfb_set_par()
1322 	t_outb(par, 0x20, VGA_ATT_W);		/* enable attr */  in tridentfb_set_par()
1342 	t_outb(par, tmp, VGA_PEL_MSK);  in tridentfb_set_par()
1371 		t_outb(par, 0xFF, VGA_PEL_MSK);  in tridentfb_setcolreg()
1372 		t_outb(par, regno, VGA_PEL_IW);  in tridentfb_setcolreg()
1374 		t_outb(par, red >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1375 		t_outb(par, green >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1376 		t_outb(par, blue >> 10, VGA_PEL_D);  in tridentfb_setcolreg()
1406 	t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */  in tridentfb_blank()
1435 	t_outb(par, 4, 0x83C8);  in tridentfb_blank()
1436 	t_outb(par, PMCont, 0x83C6);  in tridentfb_blank()