Lines Matching refs:TGA_WRITE_REG
284 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
290 TGA_WRITE_REG(par, deep_presets[tga_type] |
298 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
299 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
300 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
306 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
307 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
310 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
311 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
327 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
330 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
332 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
334 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
336 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
352 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
355 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
356 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
357 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
358 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
381 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
387 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
388 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
389 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
395 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
396 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
397 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
398 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
404 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
408 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
411 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
414 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
415 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
416 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
422 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
445 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
457 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
458 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
461 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
464 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
465 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
468 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
469 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
472 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
473 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
476 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
477 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
478 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
479 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
480 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
481 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
508 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
510 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
512 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
513 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
542 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
543 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
544 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
545 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
548 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
549 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
550 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
551 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
558 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
559 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
560 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
561 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
590 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
591 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
594 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
598 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
603 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
604 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
609 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
610 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
615 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
616 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
617 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);