Lines Matching +full:io +full:- +full:multiplex
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
30 #include <linux/i2c-algo-bit.h>
48 /* ------------------------------------------------------------------------- */
148 /* ------------------------------------------------------------------------- */
158 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
163 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
165 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
167 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
173 /* ------------------------------------------------------------------------- */
194 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_read()
195 return readb(par->mmio + DDC_MMIO_REG); in s3fb_ddc_read()
197 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
202 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_write()
203 writeb(val, par->mmio + DDC_MMIO_REG); in s3fb_ddc_write()
205 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
250 struct s3fb_info *par = info->par; in s3fb_setup_ddc_bus()
252 strscpy(par->ddc_adapter.name, info->fix.id, in s3fb_setup_ddc_bus()
253 sizeof(par->ddc_adapter.name)); in s3fb_setup_ddc_bus()
254 par->ddc_adapter.owner = THIS_MODULE; in s3fb_setup_ddc_bus()
255 par->ddc_adapter.algo_data = &par->ddc_algo; in s3fb_setup_ddc_bus()
256 par->ddc_adapter.dev.parent = info->device; in s3fb_setup_ddc_bus()
257 par->ddc_algo.setsda = s3fb_ddc_setsda; in s3fb_setup_ddc_bus()
258 par->ddc_algo.setscl = s3fb_ddc_setscl; in s3fb_setup_ddc_bus()
259 par->ddc_algo.getsda = s3fb_ddc_getsda; in s3fb_setup_ddc_bus()
260 par->ddc_algo.getscl = s3fb_ddc_getscl; in s3fb_setup_ddc_bus()
261 par->ddc_algo.udelay = 10; in s3fb_setup_ddc_bus()
262 par->ddc_algo.timeout = 20; in s3fb_setup_ddc_bus()
263 par->ddc_algo.data = par; in s3fb_setup_ddc_bus()
265 i2c_set_adapdata(&par->ddc_adapter, par); in s3fb_setup_ddc_bus()
269 * DDC and extension pins - switch it do DDC in s3fb_setup_ddc_bus()
271 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */ in s3fb_setup_ddc_bus()
272 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_setup_ddc_bus()
273 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_setup_ddc_bus()
274 par->chip == CHIP_260_VIRGE_MX) in s3fb_setup_ddc_bus()
275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); in s3fb_setup_ddc_bus()
277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); in s3fb_setup_ddc_bus()
279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); in s3fb_setup_ddc_bus()
281 return i2c_bit_add_bus(&par->ddc_adapter); in s3fb_setup_ddc_bus()
286 /* ------------------------------------------------------------------------- */
292 const u8 *font = map->data; in s3fb_settile_fast()
293 u8 __iomem *fb = (u8 __iomem *) info->screen_base; in s3fb_settile_fast()
296 if ((map->width != 8) || (map->height != 16) || in s3fb_settile_fast()
297 (map->depth != 1) || (map->length != 256)) { in s3fb_settile_fast()
299 map->width, map->height, map->depth, map->length); in s3fb_settile_fast()
304 for (i = 0; i < map->height; i++) { in s3fb_settile_fast()
305 for (c = 0; c < map->length; c++) { in s3fb_settile_fast()
306 fb_writeb(font[c * map->height + i], fb + c * 4); in s3fb_settile_fast()
314 struct s3fb_info *par = info->par; in s3fb_tilecursor()
316 svga_tilecursor(par->state.vgabase, info, cursor); in s3fb_tilecursor()
338 /* ------------------------------------------------------------------------- */
340 /* image data is MSB-first, fb structure is MSB-first too */
346 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
349 u32 fg = expand_color(image->fg_color); in s3fb_iplan_imageblit()
350 u32 bg = expand_color(image->bg_color); in s3fb_iplan_imageblit()
357 src1 = image->data; in s3fb_iplan_imageblit()
358 dst1 = info->screen_base + (image->dy * info->fix.line_length) in s3fb_iplan_imageblit()
359 + ((image->dx / 8) * 4); in s3fb_iplan_imageblit()
361 for (y = 0; y < image->height; y++) { in s3fb_iplan_imageblit()
364 for (x = 0; x < image->width; x += 8) { in s3fb_iplan_imageblit()
369 src1 += image->width / 8; in s3fb_iplan_imageblit()
370 dst1 += info->fix.line_length; in s3fb_iplan_imageblit()
375 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
378 u32 fg = expand_color(rect->color); in s3fb_iplan_fillrect()
383 dst1 = info->screen_base + (rect->dy * info->fix.line_length) in s3fb_iplan_fillrect()
384 + ((rect->dx / 8) * 4); in s3fb_iplan_fillrect()
386 for (y = 0; y < rect->height; y++) { in s3fb_iplan_fillrect()
388 for (x = 0; x < rect->width; x += 8) { in s3fb_iplan_fillrect()
391 dst1 += info->fix.line_length; in s3fb_iplan_fillrect()
396 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
403 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
406 u32 fg = image->fg_color * 0x11111111; in s3fb_cfb4_imageblit()
407 u32 bg = image->bg_color * 0x11111111; in s3fb_cfb4_imageblit()
414 src1 = image->data; in s3fb_cfb4_imageblit()
415 dst1 = info->screen_base + (image->dy * info->fix.line_length) in s3fb_cfb4_imageblit()
416 + ((image->dx / 8) * 4); in s3fb_cfb4_imageblit()
418 for (y = 0; y < image->height; y++) { in s3fb_cfb4_imageblit()
421 for (x = 0; x < image->width; x += 8) { in s3fb_cfb4_imageblit()
426 src1 += image->width / 8; in s3fb_cfb4_imageblit()
427 dst1 += info->fix.line_length; in s3fb_cfb4_imageblit()
433 if ((info->var.bits_per_pixel == 4) && (image->depth == 1) in s3fb_imageblit()
434 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { in s3fb_imageblit()
435 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) in s3fb_imageblit()
445 if ((info->var.bits_per_pixel == 4) in s3fb_fillrect()
446 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) in s3fb_fillrect()
447 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) in s3fb_fillrect()
455 /* ------------------------------------------------------------------------- */
460 struct s3fb_info *par = info->par; in s3_set_pixclock()
465 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, in s3_set_pixclock()
466 1000000000 / pixclock, &m, &n, &r, info->node); in s3_set_pixclock()
473 regval = vga_r(par->state.vgabase, VGA_MIS_R); in s3_set_pixclock()
474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in s3_set_pixclock()
477 if (par->chip == CHIP_357_VIRGE_GX2 || in s3_set_pixclock()
478 par->chip == CHIP_359_VIRGE_GX2P || in s3_set_pixclock()
479 par->chip == CHIP_360_TRIO3D_1X || in s3_set_pixclock()
480 par->chip == CHIP_362_TRIO3D_2X || in s3_set_pixclock()
481 par->chip == CHIP_368_TRIO3D_2X || in s3_set_pixclock()
482 par->chip == CHIP_260_VIRGE_MX) { in s3_set_pixclock()
483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ in s3_set_pixclock()
484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ in s3_set_pixclock()
486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); in s3_set_pixclock()
487 vga_wseq(par->state.vgabase, 0x13, m - 2); in s3_set_pixclock()
491 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ in s3_set_pixclock()
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
503 struct s3fb_info *par = info->par; in s3fb_open()
505 mutex_lock(&(par->open_lock)); in s3fb_open()
506 if (par->ref_count == 0) { in s3fb_open()
507 void __iomem *vgabase = par->state.vgabase; in s3fb_open()
509 memset(&(par->state), 0, sizeof(struct vgastate)); in s3fb_open()
510 par->state.vgabase = vgabase; in s3fb_open()
511 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; in s3fb_open()
512 par->state.num_crtc = 0x70; in s3fb_open()
513 par->state.num_seq = 0x20; in s3fb_open()
514 save_vga(&(par->state)); in s3fb_open()
517 par->ref_count++; in s3fb_open()
518 mutex_unlock(&(par->open_lock)); in s3fb_open()
527 struct s3fb_info *par = info->par; in s3fb_release()
529 mutex_lock(&(par->open_lock)); in s3fb_release()
530 if (par->ref_count == 0) { in s3fb_release()
531 mutex_unlock(&(par->open_lock)); in s3fb_release()
532 return -EINVAL; in s3fb_release()
535 if (par->ref_count == 1) in s3fb_release()
536 restore_vga(&(par->state)); in s3fb_release()
538 par->ref_count--; in s3fb_release()
539 mutex_unlock(&(par->open_lock)); in s3fb_release()
548 struct s3fb_info *par = info->par; in s3fb_check_var()
552 if (!var->pixclock) in s3fb_check_var()
553 return -EINVAL; in s3fb_check_var()
560 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) in s3fb_check_var()
561 rv = -EINVAL; in s3fb_check_var()
569 if (var->xres > var->xres_virtual) in s3fb_check_var()
570 var->xres_virtual = var->xres; in s3fb_check_var()
572 if (var->yres > var->yres_virtual) in s3fb_check_var()
573 var->yres_virtual = var->yres; in s3fb_check_var()
576 step = s3fb_formats[rv].xresstep - 1; in s3fb_check_var()
577 var->xres_virtual = (var->xres_virtual+step) & ~step; in s3fb_check_var()
580 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; in s3fb_check_var()
581 if (mem > info->screen_size) { in s3fb_check_var()
583 mem >> 10, (unsigned int) (info->screen_size >> 10)); in s3fb_check_var()
584 return -EINVAL; in s3fb_check_var()
587 rv = svga_check_timings (&s3_timing_regs, var, info->node); in s3fb_check_var()
593 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, in s3fb_check_var()
594 info->node); in s3fb_check_var()
607 struct s3fb_info *par = info->par; in s3fb_set_par()
608 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; in s3fb_set_par() local
609 u32 bpp = info->var.bits_per_pixel; in s3fb_set_par()
613 info->fix.ypanstep = 1; in s3fb_set_par()
614 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; in s3fb_set_par()
616 info->flags &= ~FBINFO_MISC_TILEBLITTING; in s3fb_set_par()
617 info->tileops = NULL; in s3fb_set_par()
621 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH); in s3fb_set_par()
622 set_bit(8 - 1, info->pixmap.blit_x); in s3fb_set_par()
624 bitmap_fill(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH); in s3fb_set_par()
626 bitmap_fill(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT); in s3fb_set_par()
628 offset_value = (info->var.xres_virtual * bpp) / 64; in s3fb_set_par()
629 screen_size = info->var.yres_virtual * info->fix.line_length; in s3fb_set_par()
631 info->fix.ypanstep = 16; in s3fb_set_par()
632 info->fix.line_length = 0; in s3fb_set_par()
634 info->flags |= FBINFO_MISC_TILEBLITTING; in s3fb_set_par()
635 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; in s3fb_set_par()
638 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH); in s3fb_set_par()
639 set_bit(8 - 1, info->pixmap.blit_x); in s3fb_set_par()
640 bitmap_zero(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT); in s3fb_set_par()
641 set_bit(16 - 1, info->pixmap.blit_y); in s3fb_set_par()
643 offset_value = info->var.xres_virtual / 16; in s3fb_set_par()
644 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; in s3fb_set_par()
647 info->var.xoffset = 0; in s3fb_set_par()
648 info->var.yoffset = 0; in s3fb_set_par()
649 info->var.activate = FB_ACTIVATE_NOW; in s3fb_set_par()
652 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3fb_set_par()
653 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3fb_set_par()
654 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3fb_set_par()
655 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in s3fb_set_par()
658 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_set_par()
659 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in s3fb_set_par()
662 svga_set_default_gfx_regs(par->state.vgabase); in s3fb_set_par()
663 svga_set_default_atc_regs(par->state.vgabase); in s3fb_set_par()
664 svga_set_default_seq_regs(par->state.vgabase); in s3fb_set_par()
665 svga_set_default_crt_regs(par->state.vgabase); in s3fb_set_par()
666 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); in s3fb_set_par()
667 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); in s3fb_set_par()
670 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ in s3fb_set_par()
671 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab… in s3fb_set_par()
673 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ in s3fb_set_par()
674 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ in s3fb_set_par()
675 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ in s3fb_set_par()
676 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ in s3fb_set_par()
678 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ in s3fb_set_par()
680 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ in s3fb_set_par()
682 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ in s3fb_set_par()
683 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ in s3fb_set_par()
688 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); in s3fb_set_par()
690 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
691 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
692 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
693 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
694 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
695 par->chip != CHIP_260_VIRGE_MX) { in s3fb_set_par()
696 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ in s3fb_set_par()
697 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ in s3fb_set_par()
698 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ in s3fb_set_par()
699 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ in s3fb_set_par()
702 vga_wcrt(par->state.vgabase, 0x3A, 0x35); in s3fb_set_par()
703 svga_wattr(par->state.vgabase, 0x33, 0x00); in s3fb_set_par()
705 if (info->var.vmode & FB_VMODE_DOUBLE) in s3fb_set_par()
706 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in s3fb_set_par()
708 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in s3fb_set_par()
710 if (info->var.vmode & FB_VMODE_INTERLACED) in s3fb_set_par()
711 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); in s3fb_set_par()
713 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); in s3fb_set_par()
716 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); in s3fb_set_par()
718 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); in s3fb_set_par()
720 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); in s3fb_set_par()
723 if (par->chip == CHIP_375_VIRGE_DX) { in s3fb_set_par()
724 vga_wcrt(par->state.vgabase, 0x86, 0x80); in s3fb_set_par()
725 vga_wcrt(par->state.vgabase, 0x90, 0x00); in s3fb_set_par()
729 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
730 vga_wcrt(par->state.vgabase, 0x50, 0x00); in s3fb_set_par()
731 vga_wcrt(par->state.vgabase, 0x67, 0x50); in s3fb_set_par()
733 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); in s3fb_set_par()
734 vga_wcrt(par->state.vgabase, 0x66, 0x90); in s3fb_set_par()
737 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
738 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
739 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
740 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
741 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
742 par->chip == CHIP_365_TRIO3D || in s3fb_set_par()
743 par->chip == CHIP_375_VIRGE_DX || in s3fb_set_par()
744 par->chip == CHIP_385_VIRGE_GX || in s3fb_set_par()
745 par->chip == CHIP_260_VIRGE_MX) { in s3fb_set_par()
746 dbytes = info->var.xres * ((bpp+7)/8); in s3fb_set_par()
747 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); in s3fb_set_par()
748 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); in s3fb_set_par()
750 vga_wcrt(par->state.vgabase, 0x66, 0x81); in s3fb_set_par()
753 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
754 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
755 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
756 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
757 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
758 par->chip == CHIP_260_VIRGE_MX) in s3fb_set_par()
759 vga_wcrt(par->state.vgabase, 0x34, 0x00); in s3fb_set_par()
761 vga_wcrt(par->state.vgabase, 0x34, 0x10); in s3fb_set_par()
763 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); in s3fb_set_par()
764 multiplex = 0; in s3fb_set_par()
767 /* Set mode-specific register values */ in s3fb_set_par()
771 svga_set_textmode_vga_regs(par->state.vgabase); in s3fb_set_par()
773 /* Set additional registers like in 8-bit mode */ in s3fb_set_par()
774 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
775 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
778 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
782 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); in s3fb_set_par()
787 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in s3fb_set_par()
789 /* Set additional registers like in 8-bit mode */ in s3fb_set_par()
790 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
791 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
794 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
799 /* Set additional registers like in 8-bit mode */ in s3fb_set_par()
800 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
801 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
804 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
808 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
809 if (info->var.pixclock > 20000 || in s3fb_set_par()
810 par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
811 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
812 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
813 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
814 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
815 par->chip == CHIP_260_VIRGE_MX) in s3fb_set_par()
816 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); in s3fb_set_par()
819 multiplex = 1; in s3fb_set_par()
824 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
825 if (info->var.pixclock > 20000) in s3fb_set_par()
826 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
828 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
829 } else if (par->chip == CHIP_365_TRIO3D) { in s3fb_set_par()
830 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
831 if (info->var.pixclock > 8695) { in s3fb_set_par()
832 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
835 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
836 multiplex = 1; in s3fb_set_par()
839 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
840 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
841 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
842 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
843 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
844 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
845 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
846 par->chip != CHIP_260_VIRGE_MX) in s3fb_set_par()
852 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
853 if (info->var.pixclock > 20000) in s3fb_set_par()
854 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
856 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
857 } else if (par->chip == CHIP_365_TRIO3D) { in s3fb_set_par()
858 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
859 if (info->var.pixclock > 8695) { in s3fb_set_par()
860 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
863 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
864 multiplex = 1; in s3fb_set_par()
867 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
868 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
869 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
870 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
871 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
872 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
873 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
874 par->chip != CHIP_260_VIRGE_MX) in s3fb_set_par()
881 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
885 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); in s3fb_set_par()
886 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
889 fb_err(info, "unsupported mode - bug\n"); in s3fb_set_par()
890 return -EINVAL; in s3fb_set_par()
893 if (par->chip != CHIP_988_VIRGE_VX) { in s3fb_set_par()
894 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); in s3fb_set_par()
895 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); in s3fb_set_par()
898 s3_set_pixclock(info, info->var.pixclock); in s3fb_set_par()
899 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, in s3fb_set_par()
900 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, in s3fb_set_par()
901 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, in s3fb_set_par()
902 hmul, info->node); in s3fb_set_par()
905 htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; in s3fb_set_par()
906 htotal = ((htotal * hmul) / 8) - 5; in s3fb_set_par()
907 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); in s3fb_set_par()
910 hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8; in s3fb_set_par()
913 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); in s3fb_set_par()
915 if (screen_size > info->screen_size) in s3fb_set_par()
916 screen_size = info->screen_size; in s3fb_set_par()
917 memset_io(info->screen_base, 0x00, screen_size); in s3fb_set_par()
919 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in s3fb_set_par()
920 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_set_par()
930 switch (fb->var.bits_per_pixel) { in s3fb_setcolreg()
934 return -EINVAL; in s3fb_setcolreg()
936 if ((fb->var.bits_per_pixel == 4) && in s3fb_setcolreg()
937 (fb->var.nonstd == 0)) { in s3fb_setcolreg()
950 return -EINVAL; in s3fb_setcolreg()
962 if (fb->var.green.length == 5) in s3fb_setcolreg()
963 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | in s3fb_setcolreg()
965 else if (fb->var.green.length == 6) in s3fb_setcolreg()
966 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | in s3fb_setcolreg()
968 else return -EINVAL; in s3fb_setcolreg()
975 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | in s3fb_setcolreg()
979 return -EINVAL; in s3fb_setcolreg()
990 struct s3fb_info *par = info->par; in s3fb_blank()
995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
996 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_blank()
1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); in s3fb_blank()
1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1010 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); in s3fb_blank()
1011 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1015 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); in s3fb_blank()
1016 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1028 struct s3fb_info *par = info->par; in s3fb_pan_display()
1032 if (info->var.bits_per_pixel == 0) { in s3fb_pan_display()
1033 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2) in s3fb_pan_display()
1034 + (var->xoffset / 2); in s3fb_pan_display()
1037 offset = (var->yoffset * info->fix.line_length) + in s3fb_pan_display()
1038 (var->xoffset * info->var.bits_per_pixel / 8); in s3fb_pan_display()
1043 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); in s3fb_pan_display()
1048 /* ------------------------------------------------------------------------- */
1069 /* ------------------------------------------------------------------------- */
1073 int chip = par->chip; in s3_identification()
1076 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification()
1077 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); in s3_identification()
1078 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); in s3_identification()
1093 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1102 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1111 switch (vga_rcrt(par->state.vgabase, 0x2f)) { in s3_identification()
1139 dev_info(&(dev->dev), "ignoring secondary device\n"); in s3_pci_probe()
1140 return -ENODEV; in s3_pci_probe()
1148 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); in s3_pci_probe()
1150 return -ENOMEM; in s3_pci_probe()
1152 par = info->par; in s3_pci_probe()
1153 mutex_init(&par->open_lock); in s3_pci_probe()
1155 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; in s3_pci_probe()
1156 info->fbops = &s3fb_ops; in s3_pci_probe()
1161 dev_err(info->device, "cannot enable PCI device\n"); in s3_pci_probe()
1167 dev_err(info->device, "cannot reserve framebuffer region\n"); in s3_pci_probe()
1172 info->fix.smem_start = pci_resource_start(dev, 0); in s3_pci_probe()
1173 info->fix.smem_len = pci_resource_len(dev, 0); in s3_pci_probe()
1175 /* Map physical IO memory address into kernel space */ in s3_pci_probe()
1176 info->screen_base = pci_iomap_wc(dev, 0, 0); in s3_pci_probe()
1177 if (! info->screen_base) { in s3_pci_probe()
1178 rc = -ENOMEM; in s3_pci_probe()
1179 dev_err(info->device, "iomap for framebuffer failed\n"); in s3_pci_probe()
1188 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); in s3_pci_probe()
1190 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; in s3_pci_probe()
1193 cr38 = vga_rcrt(par->state.vgabase, 0x38); in s3_pci_probe()
1194 cr39 = vga_rcrt(par->state.vgabase, 0x39); in s3_pci_probe()
1195 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3_pci_probe()
1196 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3_pci_probe()
1197 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3_pci_probe()
1200 par->chip = id->driver_data & CHIP_MASK; in s3_pci_probe()
1201 par->rev = vga_rcrt(par->state.vgabase, 0x2f); in s3_pci_probe()
1202 if (par->chip & CHIP_UNDECIDED_FLAG) in s3_pci_probe()
1203 par->chip = s3_identification(par); in s3_pci_probe()
1207 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1208 if (par->chip == CHIP_360_TRIO3D_1X || in s3_pci_probe()
1209 par->chip == CHIP_362_TRIO3D_2X || in s3_pci_probe()
1210 par->chip == CHIP_368_TRIO3D_2X || in s3_pci_probe()
1211 par->chip == CHIP_365_TRIO3D) { in s3_pci_probe()
1213 case 0: /* 8MB -- only 4MB usable for display */ in s3_pci_probe()
1214 case 1: /* 4MB with 32-bit bus */ in s3_pci_probe()
1216 info->screen_size = 4 << 20; in s3_pci_probe()
1220 info->screen_size = 2 << 20; in s3_pci_probe()
1223 } else if (par->chip == CHIP_357_VIRGE_GX2 || in s3_pci_probe()
1224 par->chip == CHIP_359_VIRGE_GX2P || in s3_pci_probe()
1225 par->chip == CHIP_260_VIRGE_MX) { in s3_pci_probe()
1228 info->screen_size = 4 << 20; in s3_pci_probe()
1231 info->screen_size = 2 << 20; in s3_pci_probe()
1234 } else if (par->chip == CHIP_988_VIRGE_VX) { in s3_pci_probe()
1237 info->screen_size = 2 << 20; in s3_pci_probe()
1240 info->screen_size = 4 << 20; in s3_pci_probe()
1243 info->screen_size = 6 << 20; in s3_pci_probe()
1246 info->screen_size = 8 << 20; in s3_pci_probe()
1249 /* off-screen memory */ in s3_pci_probe()
1250 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1253 info->screen_size -= 4 << 20; in s3_pci_probe()
1256 info->screen_size -= 2 << 20; in s3_pci_probe()
1260 info->screen_size = s3_memsizes[regval >> 5] << 10; in s3_pci_probe()
1261 info->fix.smem_len = info->screen_size; in s3_pci_probe()
1264 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1265 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1266 par->mclk_freq = par->mclk_freq >> (regval >> 5); in s3_pci_probe()
1269 vga_wcrt(par->state.vgabase, 0x38, cr38); in s3_pci_probe()
1270 vga_wcrt(par->state.vgabase, 0x39, cr39); in s3_pci_probe()
1272 strcpy(info->fix.id, s3_names [par->chip]); in s3_pci_probe()
1273 info->fix.mmio_start = 0; in s3_pci_probe()
1274 info->fix.mmio_len = 0; in s3_pci_probe()
1275 info->fix.type = FB_TYPE_PACKED_PIXELS; in s3_pci_probe()
1276 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in s3_pci_probe()
1277 info->fix.ypanstep = 0; in s3_pci_probe()
1278 info->fix.accel = FB_ACCEL_NONE; in s3_pci_probe()
1279 info->pseudo_palette = (void*) (par->pseudo_palette); in s3_pci_probe()
1280 info->var.bits_per_pixel = 8; in s3_pci_probe()
1284 if (s3fb_ddc_needs_mmio(par->chip)) { in s3_pci_probe()
1285 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE); in s3_pci_probe()
1286 if (par->mmio) in s3_pci_probe()
1287 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ in s3_pci_probe()
1289 dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC", in s3_pci_probe()
1290 info->fix.smem_start + MMIO_OFFSET); in s3_pci_probe()
1292 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio) in s3_pci_probe()
1294 u8 *edid = fb_ddc_read(&par->ddc_adapter); in s3_pci_probe()
1295 par->ddc_registered = true; in s3_pci_probe()
1297 fb_edid_to_monspecs(edid, &info->monspecs); in s3_pci_probe()
1299 if (!info->monspecs.modedb) in s3_pci_probe()
1300 dev_err(info->device, "error getting mode database\n"); in s3_pci_probe()
1304 fb_videomode_to_modelist(info->monspecs.modedb, in s3_pci_probe()
1305 info->monspecs.modedb_len, in s3_pci_probe()
1306 &info->modelist); in s3_pci_probe()
1307 m = fb_find_best_display(&info->monspecs, &info->modelist); in s3_pci_probe()
1309 fb_videomode_to_var(&info->var, m); in s3_pci_probe()
1310 /* fill all other info->var's fields */ in s3_pci_probe()
1311 if (s3fb_check_var(&info->var, info) == 0) in s3_pci_probe()
1319 mode_option = "640x480-8@60"; in s3_pci_probe()
1323 rc = fb_find_mode(&info->var, info, mode_option, in s3_pci_probe()
1324 info->monspecs.modedb, info->monspecs.modedb_len, in s3_pci_probe()
1325 NULL, info->var.bits_per_pixel); in s3_pci_probe()
1327 rc = -EINVAL; in s3_pci_probe()
1328 dev_err(info->device, "mode %s not found\n", mode_option); in s3_pci_probe()
1329 fb_destroy_modedb(info->monspecs.modedb); in s3_pci_probe()
1330 info->monspecs.modedb = NULL; in s3_pci_probe()
1335 fb_destroy_modedb(info->monspecs.modedb); in s3_pci_probe()
1336 info->monspecs.modedb = NULL; in s3_pci_probe()
1339 info->var.yres_virtual = info->fix.smem_len * 8 / in s3_pci_probe()
1340 (info->var.bits_per_pixel * info->var.xres_virtual); in s3_pci_probe()
1341 if (info->var.yres_virtual < info->var.yres) { in s3_pci_probe()
1342 dev_err(info->device, "virtual vertical size smaller than real\n"); in s3_pci_probe()
1343 rc = -EINVAL; in s3_pci_probe()
1347 rc = fb_alloc_cmap(&info->cmap, 256, 0); in s3_pci_probe()
1349 dev_err(info->device, "cannot allocate colormap\n"); in s3_pci_probe()
1355 dev_err(info->device, "cannot register framebuffer\n"); in s3_pci_probe()
1360 info->fix.id, pci_name(dev), in s3_pci_probe()
1361 info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); in s3_pci_probe()
1363 if (par->chip == CHIP_UNKNOWN) in s3_pci_probe()
1365 vga_rcrt(par->state.vgabase, 0x2d), in s3_pci_probe()
1366 vga_rcrt(par->state.vgabase, 0x2e), in s3_pci_probe()
1367 vga_rcrt(par->state.vgabase, 0x2f), in s3_pci_probe()
1368 vga_rcrt(par->state.vgabase, 0x30)); in s3_pci_probe()
1374 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, in s3_pci_probe()
1375 info->fix.smem_len); in s3_pci_probe()
1381 fb_dealloc_cmap(&info->cmap); in s3_pci_probe()
1385 if (par->ddc_registered) in s3_pci_probe()
1386 i2c_del_adapter(&par->ddc_adapter); in s3_pci_probe()
1387 if (par->mmio) in s3_pci_probe()
1388 iounmap(par->mmio); in s3_pci_probe()
1390 pci_iounmap(dev, info->screen_base); in s3_pci_probe()
1409 par = info->par; in s3_pci_remove()
1410 arch_phys_wc_del(par->wc_cookie); in s3_pci_remove()
1412 fb_dealloc_cmap(&info->cmap); in s3_pci_remove()
1415 if (par->ddc_registered) in s3_pci_remove()
1416 i2c_del_adapter(&par->ddc_adapter); in s3_pci_remove()
1417 if (par->mmio) in s3_pci_remove()
1418 iounmap(par->mmio); in s3_pci_remove()
1421 pci_iounmap(dev, info->screen_base); in s3_pci_remove()
1434 struct s3fb_info *par = info->par; in s3_pci_suspend()
1436 dev_info(info->device, "suspend\n"); in s3_pci_suspend()
1439 mutex_lock(&(par->open_lock)); in s3_pci_suspend()
1441 if (par->ref_count == 0) { in s3_pci_suspend()
1442 mutex_unlock(&(par->open_lock)); in s3_pci_suspend()
1449 mutex_unlock(&(par->open_lock)); in s3_pci_suspend()
1461 struct s3fb_info *par = info->par; in s3_pci_resume()
1463 dev_info(info->device, "resume\n"); in s3_pci_resume()
1466 mutex_lock(&(par->open_lock)); in s3_pci_resume()
1468 if (par->ref_count == 0) { in s3_pci_resume()
1469 mutex_unlock(&(par->open_lock)); in s3_pci_resume()
1477 mutex_unlock(&(par->open_lock)); in s3_pci_resume()
1572 return -ENODEV; in s3fb_init()
1576 return -ENODEV; in s3fb_init()
1584 /* ------------------------------------------------------------------------- */