Lines Matching refs:memory_width

193   int memory_width;
214   int memory_width;
235   int memory_width;
272             ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
284             ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
343                 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
359                 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
369                 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
380         ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
387         ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
437     eburst_size = state->memory_width * 1;
453         ens =  1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
465         mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
480         gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
492         vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
630     sim_data.memory_width   = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
632     sim_data.memory_width   = 128;
674     width = arb->memory_width >> 6;
817     sim_data.memory_width   = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
860     width = arb->memory_width/64;
884       if (arb->memory_width == 64) /* 64 bit bus */
889       if (arb->memory_width == 64) /* 64 bit bus */
894     if ((!video_enable) && (arb->memory_width == 128))
1068     sim_data.memory_width   = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1125     sim_data.memory_width   = 64;