Lines Matching +full:enable +full:- +full:bias +full:- +full:control
1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define LCCR0 (0x000) /* LCD Controller Control Register 0 */
9 #define LCCR1 (0x004) /* LCD Controller Control Register 1 */
10 #define LCCR2 (0x008) /* LCD Controller Control Register 2 */
11 #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
12 #define LCCR4 (0x010) /* LCD Controller Control Register 4 */
13 #define LCCR5 (0x014) /* LCD Controller Control Register 5 */
18 #define TMEDCR (0x044) /* TMED Control Register */
28 #define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */
29 #define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */
30 #define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */
31 #define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */
33 #define CMDCR (0x100) /* Command Control Register */
57 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
84 #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
85 #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
99 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
100 #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
102 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
103 #define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP))
105 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */
106 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
108 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
111 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
114 #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
119 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
120 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
122 #define LCCR3_OEP (1 << 23) /* Output Enable Polarity */
123 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
124 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
130 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
147 #define LCSR_ABC (1 << 3) /* AC Bias count */
161 #define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */
165 /* overlay control registers */
166 #define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */
167 #define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */
169 #define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */