Lines Matching +full:bits +full:- +full:per +full:- +full:pixel

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * LCD Controller Registers and Bits Definitions
72 #define LCCR0_DPD	(1 << 9)	/* Double Pixel Data (monochrome) */
73 #define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome display */
90 #define LCCR1_PPL	Fld (10, 0)	/* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel)	(((Pixel) - 1) << FShft (LCCR1_PPL))  argument
94 #define LCCR1_HorSnchWdth(Tpix)	(((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix)	(((Tpix) - 1) << FShft (LCCR1_ELW))
99 #define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock */
100 #define LCCR1_BegLnDel(Tpix)	(((Tpix) - 1) << FShft (LCCR1_BLW))
102 #define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1 */
103 #define LCCR2_DisHght(Line)	(((Line) - 1) << FShft (LCCR2_LPP))
105 #define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse - 1 */
106 #define LCCR2_VrtSnchWdth(Tln)	(((Tln) - 1) << FShft (LCCR2_VSW))
108 #define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait */
111 #define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock */
114 #define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
118 #define LCCR3_PCP	(1 << 22)	/* Pixel Clock Polarity (L_PCLK) */
119 #define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge */
120 #define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge */
126 #define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
127 #define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor */
161 #define LCSR1_SOF(x)	(1 << ((x) - 1))  /* Start of Frame Status */
166 #define OVLxC1_PPL(x)	((((x) - 1) & 0x3ff) << 0)	/* Pixels Per Line */
167 #define OVLxC1_LPO(x)	((((x) - 1) & 0x3ff) << 10)	/* Number of Lines */
168 #define OVLxC1_BPP(x)	(((x) & 0xf) << 20)	/* Bits Per Pixel */
172 #define OVL2C2_PFOR(x)	(((x) & 0x7) << 20)	/* Pixel Format */