Lines Matching refs:REG_GET
111 #define REG_GET(dsidev, idx, start, end) \ macro
502 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
509 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1784 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
2280 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); in dsi_vc_is_enabled()
2291 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) in dsi_packet_sent_handler_vp()
2314 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { in dsi_sync_vc_vp()
2341 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) in dsi_packet_sent_handler_l4()
2360 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { in dsi_sync_vc_l4()
2513 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_long_data()
2565 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_receive_data()
2601 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_send_bta()
2853 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_write_common()
2946 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { in dsi_vc_read_rx_fifo()
3129 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { in dsi_enter_ulps()
3147 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ in dsi_enter_ulps()
3152 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ in dsi_enter_ulps()
5422 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); in dsi_bind()