Lines Matching full:tv
18 /* TV patch register for MMP2 */
19 /* 32 bit TV Video Frame0 Y Starting Address */
21 /* 32 bit TV Video Frame0 U Starting Address */
23 /* 32 bit TV Video Frame0 V Starting Address */
25 /* 32 bit TV Video Frame0 Command Starting Address */
27 /* 32 bit TV Video Frame1 Y Starting Address Register*/
29 /* 32 bit TV Video Frame1 U Starting Address Register*/
31 /* 32 bit TV Video Frame1 V Starting Address Register*/
33 /* 32 bit TV Video Frame1 Command Starting Address Register*/
35 /* 32 bit TV Video Y andC Line Length(Pitch)Register*/
37 /* 32 bit TV Video U andV Line Length(Pitch)Register*/
39 /* 32 bit TV Video Starting Point on Screen Register*/
41 /* 32 bit TV Video Source Size Register*/
43 /* 32 bit TV Video Destination Size (After Zooming)Register*/
59 /* 32 bit TV Graphic Frame 0 Starting Address Register*/
61 /* 32 bit TV Graphic Frame 1 Starting Address Register*/
63 /* 32 bit TV Graphic Line Length(Pitch)Register*/
65 /* 32 bit TV Graphic Starting Point on Screen Register*/
67 /* 32 bit TV Graphic Source Size Register*/
69 /* 32 bit TV Graphic Destination size (after Zooming)Register*/
78 /* 32 bit TV Hardware Cursor Starting Point on screen Register*/
80 /* 32 bit TV Hardware Cursor Size Register */
85 /* 32 bit TV Total Screen Size Register*/
87 /* 32 bit TV Screen Active Size Register*/
89 /* 32 bit TV Screen Horizontal Porch Register*/
91 /* 32 bit TV Screen Vertical Porch Register*/
98 /* 32 bit TV Screen Blank Color Register*/
100 /* 32 bit TV Hardware Cursor Color1 Register*/
102 /* 32 bit TV Hardware Cursor Color2 Register*/
108 /* 32 bit TV Video Y Color Key Control*/
110 /* 32 bit TV Video U Color Key Control*/
112 /* 32 bit TV Video V Color Key Control*/
118 /* 32 bit TV VSYNC PulsePixel Edge Control Register*/
131 /* 32 bit TV Path DMA Control 0*/
133 /* 32 bit TV Path DMA Control 1*/
135 /* 32 bit TV Path Video Contrast*/
137 /* 32 bit TV Path Video Saturation*/
139 /* 32 bit TV Path Video Hue Adjust*/
141 /* 32 bit TV Path TVIF Control Register */
145 /* 32 bit TV Path I/O Pad Control*/
147 /* 32 bit TV Path Cloc Divider */
833 /* 32 bit TV Path Graphic Partial Display Horizontal Control Register*/
835 /* 32 bit TV Path Graphic Partial Display Vertical Control Register*/