Lines Matching refs:minfo
94 void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
101 int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
191 int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
198 struct matrox_hw_state * const hw = &minfo->hw;
248 divider = minfo->curr.final_bppShift;
278 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
295 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
339 void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
342 struct matrox_hw_state * const hw = &minfo->hw;
531 static int parse_pins1(struct matrox_fb_info *minfo,
544 minfo->limits.pixel.vcomax = maxdac;
545 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
548 minfo->features.pll.ref_freq = 14318;
549 minfo->values.reg.mctlwtst = 0x00030101;
553 static void default_pins1(struct matrox_fb_info *minfo)
556 minfo->limits.pixel.vcomax = 220000;
557 minfo->values.pll.system = 50000;
558 minfo->features.pll.ref_freq = 14318;
559 minfo->values.reg.mctlwtst = 0x00030101;
562 static int parse_pins2(struct matrox_fb_info *minfo,
565 minfo->limits.pixel.vcomax =
566 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
567 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
571 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
572 minfo->features.pll.ref_freq = 14318;
576 static void default_pins2(struct matrox_fb_info *minfo)
579 minfo->limits.pixel.vcomax =
580 minfo->limits.system.vcomax = 230000;
581 minfo->values.reg.mctlwtst = 0x00030101;
582 minfo->values.pll.system = 50000;
583 minfo->features.pll.ref_freq = 14318;
586 static int parse_pins3(struct matrox_fb_info *minfo,
589 minfo->limits.pixel.vcomax =
590 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
591 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
594 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
598 minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
599 minfo->values.reg.opt2 = bd->pins[58] << 12;
600 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
604 static void default_pins3(struct matrox_fb_info *minfo)
607 minfo->limits.pixel.vcomax =
608 minfo->limits.system.vcomax = 230000;
609 minfo->values.reg.mctlwtst = 0x01250A21;
610 minfo->values.reg.memrdbk = 0x00000000;
611 minfo->values.reg.opt = 0x00000C00;
612 minfo->values.reg.opt2 = 0x00000000;
613 minfo->features.pll.ref_freq = 27000;
616 static int parse_pins4(struct matrox_fb_info *minfo,
619 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
620 minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
621 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
622 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
626 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
629 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
630 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
631 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
635 static void default_pins4(struct matrox_fb_info *minfo)
638 minfo->limits.pixel.vcomax =
639 minfo->limits.system.vcomax = 252000;
640 minfo->values.reg.mctlwtst = 0x04A450A1;
641 minfo->values.reg.memrdbk = 0x000000E7;
642 minfo->values.reg.opt = 0x10000400;
643 minfo->values.reg.opt3 = 0x0190A419;
644 minfo->values.pll.system = 200000;
645 minfo->features.pll.ref_freq = 27000;
648 static int parse_pins5(struct matrox_fb_info *minfo,
655 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
656 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
657 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
658 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
659 minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
660 minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
661 minfo->values.pll.system =
662 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
663 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
664 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
665 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
666 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
667 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
668 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
669 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
670 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
671 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
672 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
673 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
675 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
681 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
682 wtst_xlat[minfo->values.reg.mctlwtst & 7];
684 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
688 static void default_pins5(struct matrox_fb_info *minfo)
691 minfo->limits.pixel.vcomax =
692 minfo->limits.system.vcomax =
693 minfo->limits.video.vcomax = 600000;
694 minfo->limits.pixel.vcomin =
695 minfo->limits.system.vcomin =
696 minfo->limits.video.vcomin = 256000;
697 minfo->values.pll.system =
698 minfo->values.pll.video = 284000;
699 minfo->values.reg.opt = 0x404A1160;
700 minfo->values.reg.opt2 = 0x0000AC00;
701 minfo->values.reg.opt3 = 0x0090A409;
702 minfo->values.reg.mctlwtst_core =
703 minfo->values.reg.mctlwtst = 0x0C81462B;
704 minfo->values.reg.memmisc = 0x80000004;
705 minfo->values.reg.memrdbk = 0x01001103;
706 minfo->features.pll.ref_freq = 27000;
707 minfo->values.memory.ddr = 1;
708 minfo->values.memory.dll = 1;
709 minfo->values.memory.emrswen = 1;
710 minfo->values.reg.maccess = 0x00004000;
713 static int matroxfb_set_limits(struct matrox_fb_info *minfo,
719 switch (minfo->chip) {
720 case MGA_2064: default_pins1(minfo); break;
723 case MGA_1164: default_pins2(minfo); break;
725 case MGA_G200: default_pins3(minfo); break;
726 case MGA_G400: default_pins4(minfo); break;
728 case MGA_G550: default_pins5(minfo); break;
753 return parse_pins1(minfo, bd);
755 return parse_pins2(minfo, bd);
757 return parse_pins3(minfo, bd);
759 return parse_pins4(minfo, bd);
761 return parse_pins5(minfo, bd);
768 void matroxfb_read_pins(struct matrox_fb_info *minfo)
773 struct pci_dev *pdev = minfo->pcidev;
775 memset(&minfo->bios, 0, sizeof(minfo->bios));
779 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
781 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
785 if (!minfo->bios.bios_valid) {
799 parse_bios(b, &minfo->bios);
805 matroxfb_set_limits(minfo, &minfo->bios);
807 (minfo->values.reg.opt & 0x1C00) >> 10);