Lines Matching refs:minfo

38 static void DAC1064_calcclock(const struct matrox_fb_info *minfo,
50 fvco = PLL_calcclock(minfo, freq, fmax, in, feed, &p);
89 static void DAC1064_setpclk(struct matrox_fb_info *minfo, unsigned long fout)
95 DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p);
96 minfo->hw.DACclk[0] = m;
97 minfo->hw.DACclk[1] = n;
98 minfo->hw.DACclk[2] = p;
101 static void DAC1064_setmclk(struct matrox_fb_info *minfo, int oscinfo,
105 struct matrox_hw_state *hw = &minfo->hw;
109 if (minfo->devflags.noinit) {
111 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
112 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
113 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
117 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
132 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
134 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
143 DAC1064_calcclock(minfo, fmem, minfo->max_pixel_clock, &m, &n, &p);
144 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m);
145 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n);
146 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p);
148 if (inDAC1064(minfo, DAC1064_XSYSPLLSTAT) & 0x40)
159 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
161 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
166 static void g450_set_plls(struct matrox_fb_info *minfo)
170 struct matrox_hw_state *hw = &minfo->hw;
177 pixelmnp = minfo->crtc1.mnp;
178 videomnp = minfo->crtc2.mnp;
182 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) {
197 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
198 matroxfb_g450_setpll_cond(minfo, videomnp, M_VIDEO_PLL);
205 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
206 matroxfb_g450_setpll_cond(minfo, pixelmnp, M_PIXEL_PLL_C);
213 pxc = minfo->crtc1.pixclock;
214 if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) {
215 pxc = minfo->crtc2.pixclock;
217 if (minfo->chip == MGA_G550) {
258 void DAC1064_global_init(struct matrox_fb_info *minfo)
260 struct matrox_hw_state *hw = &minfo->hw;
266 if (minfo->devflags.g450dac) {
270 switch (minfo->outputs[0].src) {
279 switch (minfo->outputs[1].src) {
284 if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) {
294 switch (minfo->outputs[2].src) {
313 g450_set_plls(minfo);
317 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) {
320 } else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) {
322 } else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1)
327 if (minfo->outputs[0].src != MATROXFB_SRC_NONE)
332 void DAC1064_global_restore(struct matrox_fb_info *minfo)
334 struct matrox_hw_state *hw = &minfo->hw;
336 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
337 outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]);
338 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
339 outDAC1064(minfo, 0x20, 0x04);
340 outDAC1064(minfo, 0x1F, minfo->devflags.dfp_type);
341 if (minfo->devflags.g450dac) {
342 outDAC1064(minfo, M1064_XSYNCCTRL, 0xCC);
343 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
344 outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]);
345 outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]);
350 static int DAC1064_init_1(struct matrox_fb_info *minfo, struct my_timming *m)
352 struct matrox_hw_state *hw = &minfo->hw;
357 switch (minfo->fbcon.var.bits_per_pixel) {
363 if (minfo->fbcon.var.green.length == 5)
377 hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl;
383 DAC1064_global_init(minfo);
387 static int DAC1064_init_2(struct matrox_fb_info *minfo, struct my_timming *m)
389 struct matrox_hw_state *hw = &minfo->hw;
393 if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */
401 } else if (minfo->fbcon.var.bits_per_pixel > 8) {
402 if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */
430 static void DAC1064_restore_1(struct matrox_fb_info *minfo)
432 struct matrox_hw_state *hw = &minfo->hw;
440 if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) ||
441 (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) ||
442 (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) {
443 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]);
444 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]);
445 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]);
452 outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]);
456 DAC1064_global_restore(minfo);
461 static void DAC1064_restore_2(struct matrox_fb_info *minfo)
472 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]);
477 dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]);
483 #define minfo ((struct matrox_fb_info*)out)
489 DAC1064_setpclk(minfo, m->pixclock);
494 outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]);
496 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40)
506 #undef minfo
517 #define minfo ((struct matrox_fb_info*)out)
519 m->mnp = matroxfb_g450_setclk(minfo, m->pixclock, (m->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
521 m->pixclock = g450_mnp2f(minfo, m->mnp);
524 #undef minfo
537 static int MGA1064_init(struct matrox_fb_info *minfo, struct my_timming *m)
539 struct matrox_hw_state *hw = &minfo->hw;
543 if (DAC1064_init_1(minfo, m)) return 1;
544 if (matroxfb_vgaHWinit(minfo, m)) return 1;
554 if (DAC1064_init_2(minfo, m)) return 1;
560 static int MGAG100_init(struct matrox_fb_info *minfo, struct my_timming *m)
562 struct matrox_hw_state *hw = &minfo->hw;
566 if (DAC1064_init_1(minfo, m)) return 1;
568 if (matroxfb_vgaHWinit(minfo, m)) return 1;
578 if (DAC1064_init_2(minfo, m)) return 1;
584 static void MGA1064_ramdac_init(struct matrox_fb_info *minfo)
589 /* minfo->features.DAC1064.vco_freq_min = 120000; */
590 minfo->features.pll.vco_freq_min = 62000;
591 minfo->features.pll.ref_freq = 14318;
592 minfo->features.pll.feed_div_min = 100;
593 minfo->features.pll.feed_div_max = 127;
594 minfo->features.pll.in_div_min = 1;
595 minfo->features.pll.in_div_max = 31;
596 minfo->features.pll.post_shift_max = 3;
597 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL;
599 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333);
611 static void MGAG100_progPixClock(const struct matrox_fb_info *minfo, int flags,
620 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) | M1064_XPIXCLKCTRL_DIS |
627 outDAC1064(minfo, reg++, m);
628 outDAC1064(minfo, reg++, n);
629 outDAC1064(minfo, reg, p);
641 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40)
647 selClk = inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_SRC_MASK;
653 outDAC1064(minfo, M1064_XPIXCLKCTRL, selClk);
654 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_DIS);
657 static void MGAG100_setPixClock(const struct matrox_fb_info *minfo, int flags,
664 DAC1064_calcclock(minfo, freq, minfo->max_pixel_clock, &m, &n, &p);
665 MGAG100_progPixClock(minfo, flags, m, n, p);
670 static int MGA1064_preinit(struct matrox_fb_info *minfo)
675 struct matrox_hw_state *hw = &minfo->hw;
679 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
680 minfo->capable.text = 1;
681 minfo->capable.vxres = vxres_mystique;
683 minfo->outputs[0].output = &m1064;
684 minfo->outputs[0].src = minfo->outputs[0].default_src;
685 minfo->outputs[0].data = minfo;
686 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
688 if (minfo->devflags.noinit)
692 if (minfo->devflags.novga)
694 if (minfo->devflags.nobios)
696 if (minfo->devflags.nopciretry)
698 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
708 static void MGA1064_reset(struct matrox_fb_info *minfo)
713 MGA1064_ramdac_init(minfo);
718 static void g450_mclk_init(struct matrox_fb_info *minfo)
721 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
722 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03);
723 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
725 if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) ||
726 ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) ||
727 ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) {
728 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL);
734 pwr = inDAC1064(minfo, M1064_XPWRCTRL) & ~0x02;
735 outDAC1064(minfo, M1064_XPWRCTRL, pwr);
738 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL);
741 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
742 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3);
743 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
747 static void g450_memory_init(struct matrox_fb_info *minfo)
750 minfo->hw.MXoptionReg &= ~0x001F8000;
751 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
754 minfo->hw.MXoptionReg &= ~0x00207E00;
755 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt;
756 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
757 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2);
759 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
762 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U);
763 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
764 mga_outl(M_MACCESS, minfo->values.reg.maccess);
766 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U);
770 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) {
771 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000);
773 mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000);
777 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt;
778 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
784 if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) {
785 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core);
790 static void g450_preinit(struct matrox_fb_info *minfo)
796 /* minfo->hw.MXoptionReg = minfo->values.reg.opt; */
797 minfo->hw.MXoptionReg &= 0xC0000100;
798 minfo->hw.MXoptionReg |= 0x00000020;
799 if (minfo->devflags.novga)
800 minfo->hw.MXoptionReg &= ~0x00000100;
801 if (minfo->devflags.nobios)
802 minfo->hw.MXoptionReg &= ~0x40000000;
803 if (minfo->devflags.nopciretry)
804 minfo->hw.MXoptionReg |= 0x20000000;
805 minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040;
806 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
814 curctl = inDAC1064(minfo, M1064_XCURCTRL);
815 outDAC1064(minfo, M1064_XCURCTRL, 0);
820 g450_mclk_init(minfo);
821 g450_memory_init(minfo);
824 matroxfb_g450_setclk(minfo, 25175, M_PIXEL_PLL_A);
825 matroxfb_g450_setclk(minfo, 28322, M_PIXEL_PLL_B);
831 outDAC1064(minfo, M1064_XCURCTRL, curctl);
839 static int MGAG100_preinit(struct matrox_fb_info *minfo)
844 struct matrox_hw_state *hw = &minfo->hw;
854 if (minfo->devflags.g450dac) {
855 minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */
857 minfo->features.pll.vco_freq_min = 62000;
859 if (!minfo->features.pll.ref_freq) {
860 minfo->features.pll.ref_freq = 27000;
862 minfo->features.pll.feed_div_min = 7;
863 minfo->features.pll.feed_div_max = 127;
864 minfo->features.pll.in_div_min = 1;
865 minfo->features.pll.in_div_max = 31;
866 minfo->features.pll.post_shift_max = 3;
867 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT;
868 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
869 minfo->capable.text = 1;
870 minfo->capable.vxres = vxres_g100;
871 minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100
872 ? minfo->devflags.sgram : 1;
874 if (minfo->devflags.g450dac) {
875 minfo->outputs[0].output = &g450out;
877 minfo->outputs[0].output = &m1064;
879 minfo->outputs[0].src = minfo->outputs[0].default_src;
880 minfo->outputs[0].data = minfo;
881 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
883 if (minfo->devflags.g450dac) {
888 if (minfo->devflags.noinit)
890 if (minfo->devflags.g450dac) {
891 g450_preinit(minfo);
896 if (minfo->devflags.novga)
898 if (minfo->devflags.nobios)
900 if (minfo->devflags.nopciretry)
902 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
903 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333);
905 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) {
906 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, &reg50);
908 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
911 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
912 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
922 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
928 mga_writeb(minfo->video.vbase, 0x0000, 0xAA);
929 mga_writeb(minfo->video.vbase, 0x0800, 0x55);
930 mga_writeb(minfo->video.vbase, 0x4000, 0x55);
932 if (mga_readb(minfo->video.vbase, 0x0000) != 0xAA) {
937 } else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) {
938 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, &reg50);
940 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
942 if (minfo->devflags.memtype == -1)
943 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
945 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
946 if (minfo->devflags.sgram)
948 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
949 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
954 mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk);
957 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, &reg50);
960 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
962 if (minfo->devflags.memtype == -1)
963 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
965 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
966 if (minfo->devflags.sgram)
968 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
969 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
974 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
977 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
981 static void MGAG100_reset(struct matrox_fb_info *minfo)
984 struct matrox_hw_state *hw = &minfo->hw;
994 if (b == minfo->pcidev->bus->number) {
1001 if (!minfo->devflags.noinit) {
1004 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1009 if (minfo->devflags.g450dac) {
1011 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
1012 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
1013 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
1015 DAC1064_setmclk(minfo, DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_SCLK_PLL, 133333);
1017 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
1018 if (minfo->devflags.dfp_type == -1) {
1019 minfo->devflags.dfp_type = inDAC1064(minfo, 0x1F);
1022 if (minfo->devflags.noinit)
1024 if (minfo->devflags.g450dac) {
1026 MGAG100_setPixClock(minfo, 4, 25175);
1027 MGAG100_setPixClock(minfo, 5, 28322);
1029 b = inDAC1064(minfo, M1064_XGENIODATA) & ~1;
1030 outDAC1064(minfo, M1064_XGENIODATA, b);
1031 b = inDAC1064(minfo, M1064_XGENIOCTRL) | 1;
1032 outDAC1064(minfo, M1064_XGENIOCTRL, b);
1039 static void MGA1064_restore(struct matrox_fb_info *minfo)
1042 struct matrox_hw_state *hw = &minfo->hw;
1050 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1056 DAC1064_restore_1(minfo);
1057 matroxfb_vgaHWrestore(minfo);
1058 minfo->crtc1.panpos = -1;
1061 DAC1064_restore_2(minfo);
1066 static void MGAG100_restore(struct matrox_fb_info *minfo)
1069 struct matrox_hw_state *hw = &minfo->hw;
1077 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1080 DAC1064_restore_1(minfo);
1081 matroxfb_vgaHWrestore(minfo);
1082 if (minfo->devflags.support32MB)
1084 minfo->crtc1.panpos = -1;
1087 DAC1064_restore_2(minfo);