Lines Matching +full:0 +full:xe4000000
34 #define G364_MEM_BASE 0xe4400000
35 #define G364_PORT_BASE 0xe4000000
36 #define ID_REG 0xe4000000 /* Read only */
37 #define BOOT_REG 0xe4080000
38 #define TIMING_REG 0xe4080108 /* to 0x080170 - DON'T TOUCH! */
39 #define DISPLAY_REG 0xe4080118
40 #define VDISPLAY_REG 0xe4080150
41 #define MASK_REG 0xe4080200
42 #define CTLA_REG 0xe4080300
43 #define CURS_TOGGLE 0x800000
44 #define BIT_PER_PIX 0x700000 /* bits 22 to 20 of Control A */
45 #define DELAY_SAMPLE 0x080000
46 #define PORT_INTER 0x040000
47 #define PIX_PIPE_DEL 0x030000 /* bits 17 and 16 of Control A */
48 #define PIX_PIPE_DEL2 0x008000 /* same as above - don't ask me why */
49 #define TR_CYCLE_TOG 0x004000
50 #define VRAM_ADR_INC 0x003000 /* bits 13 and 12 of Control A */
51 #define BLANK_OFF 0x000800
52 #define FORCE_BLANK 0x000400
53 #define BLK_FUN_SWTCH 0x000200
54 #define BLANK_IO 0x000100
55 #define BLANK_LEVEL 0x000080
56 #define A_VID_FORM 0x000040
57 #define D_SYNC_FORM 0x000020
58 #define FRAME_FLY_PAT 0x000010
59 #define OP_MODE 0x000008
60 #define INTL_STAND 0x000004
61 #define SCRN_FORM 0x000002
62 #define ENABLE_VTG 0x000001
63 #define TOP_REG 0xe4080400
64 #define CURS_PAL_REG 0xe4080508 /* to 0x080518 */
65 #define CHKSUM_REG 0xe4080600 /* to 0x080610 - unused */
66 #define CURS_POS_REG 0xe4080638
67 #define CLR_PAL_REG 0xe4080800 /* to 0x080ff8 */
68 #define CURS_PAT_REG 0xe4081000 /* to 0x081ff8 */
69 #define MON_ID_REG 0xe4100000 /* unused */
70 #define RESET_REG 0xe4180000 /* Write only */
76 .smem_start = 0x40000000, /* physical address */
85 .red = { 0, 8, 0 },
86 .green = { 0, 8, 0 },
87 .blue = { 0, 8, 0 },
134 return 0; in g364fb_pan_display()
146 return 0; in g364fb_blank()
150 * Set a single color register. Return != 0 for invalid regno.
166 return 0; in g364fb_setcolreg()
186 (*((volatile unsigned int *) DISPLAY_REG) & 0x00ffffff) * 4; in g364fb_init()
188 (*((volatile unsigned int *) VDISPLAY_REG) & 0x00ffffff) / 2; in g364fb_init()
192 curs_pal_ptr[0] |= 0x00ffffff; in g364fb_init()
193 curs_pal_ptr[2] |= 0x00ffffff; in g364fb_init()
194 curs_pal_ptr[4] |= 0x00ffffff; in g364fb_init()
199 for (i = 0; i < 512; i++) in g364fb_init()
200 *(unsigned short *) (CURS_PAT_REG + i * 8) = 0; in g364fb_init()
206 *(unsigned short *) (CURS_PAT_REG + 14 * 64) = 0xffff; in g364fb_init()
207 *(unsigned short *) (CURS_PAT_REG + 15 * 64) = 0xffff; in g364fb_init()
210 fb_fix.smem_start = 0x40000000; /* physical address */ in g364fb_init()
222 fb_alloc_cmap(&fb_info.cmap, 255, 0); in g364fb_init()
224 if (register_framebuffer(&fb_info) < 0) in g364fb_init()
226 return 0; in g364fb_init()