Lines Matching +full:capture +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1998-2000 Russell King
67 #define EXT_BUS_CTL_PCIBURST_READ 0x80 /* CyberPro 5000 only */
80 #define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */
199 #define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */
202 #define EXT_CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */
250 #define EXT_X_START 0xc5 /* ext->screen, 16 bits */
251 #define EXT_X_END 0xc7 /* ext->screen, 16 bits */
252 #define EXT_Y_START 0xc9 /* ext->screen, 16 bits */
253 #define EXT_Y_END 0xcb /* ext->screen, 16 bits */
256 #define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */
257 #define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */
258 #define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */
259 #define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */
264 #define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */
292 #define EXT_ROM_UCB4GH_FREEZE 0x02 /* capture frozen */
299 #define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/
301 #define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */
302 #define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */
318 #define VFAC_CTL3_CAP_LARGE_FIFO 0x01 /* large capture fifo */
319 #define VFAC_CTL3_CAP_INTERLACE 0x02 /* capture odd and even fields */
320 #define VFAC_CTL3_CAP_HOLD_4NS 0x00 /* hold capture data for 4ns */
321 #define VFAC_CTL3_CAP_HOLD_2NS 0x04 /* hold capture data for 2ns */
322 #define VFAC_CTL3_CAP_HOLD_6NS 0x08 /* hold capture data for 6ns */
323 #define VFAC_CTL3_CAP_HOLD_0NS 0x0c /* hold capture data for 0ns */
324 #define VFAC_CTL3_CHROMAKEY 0x20 /* capture data will be chromakeyed */
325 #define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */
349 * Bus-master
360 #define BM_COUNT 0xbc090 /* read-only */
397 #define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/
405 * Graphics Co-processor