Lines Matching refs:div2
642 * fclock = fpll / div2
648 * div2 = 2^(reg0xb1.7:6)
658 u_int div2, t_div1, best_div1, best_mult;
664 * find div2 such that 115MHz < fpll < 260MHz
665 * and 0 <= div2 < 4
667 for (div2 = 0; div2 < 4; div2++) {
670 new_pll = pll_ps / cfb->divisors[div2];
677 if (div2 == 4)
733 hw->clock_div = div2 << 6 | (best_div1 - 1);