Lines Matching refs:pllSPLL_CNTL
661 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); in radeon_pm_save_regs()
1467 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_all_ppls_off()
1468 OUTPLL(pllSPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1482 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1483 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1494 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1495 OUTPLL(pllSPLL_CNTL, tmp & ~1); in radeon_pm_start_mclk_sclk()
1496 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1501 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1502 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1503 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1657 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1862 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M10()
2094 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M9P()