Lines Matching +full:timeout +full:- +full:ati +full:- +full:ms
4 * framebuffer driver for ATI Radeon chipset video boards
11 * Special thanks to ATI DevRel team for their hardware donations.
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
263 static int default_dynclk = -2;
281 void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) in _radeon_msleep() argument
283 if (rinfo->no_schedule || oops_in_progress) in _radeon_msleep()
284 mdelay(ms); in _radeon_msleep()
286 msleep(ms); in _radeon_msleep()
291 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ in radeon_pll_errata_after_index_slow()
298 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { in radeon_pll_errata_after_data_slow()
302 if (rinfo->errata & CHIP_ERRATA_R300_CG) { in radeon_pll_errata_after_data_slow()
317 spin_lock_irqsave(&rinfo->reg_lock, flags); in _OUTREGP()
322 spin_unlock_irqrestore(&rinfo->reg_lock, flags); in _OUTREGP()
364 printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); in _radeon_fifo_wait()
386 printk(KERN_ERR "radeonfb: Flush Timeout !\n"); in radeon_engine_flush()
403 printk(KERN_ERR "radeonfb: Idle Timeout !\n"); in _radeon_engine_idle()
410 if (!rinfo->bios_seg) in radeon_unmap_ROM()
412 pci_unmap_rom(dev, rinfo->bios_seg); in radeon_unmap_ROM()
427 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ in radeon_map_ROM()
438 pci_name(rinfo->pdev)); in radeon_map_ROM()
439 return -ENOMEM; in radeon_map_ROM()
442 rinfo->bios_seg = rom; in radeon_map_ROM()
448 pci_name(rinfo->pdev), BIOS_IN16(0)); in radeon_map_ROM()
460 * relative start of ROM, but so far, I never found a dual-image ATI card in radeon_map_ROM()
480 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr)); in radeon_map_ROM()
492 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n"); in radeon_map_ROM()
500 rinfo->fp_bios_start = BIOS_IN16(0x48); in radeon_map_ROM()
504 rinfo->bios_seg = NULL; in radeon_map_ROM()
506 return -ENXIO; in radeon_map_ROM()
523 return -ENOMEM; in radeon_find_mem_vbios()
530 return -ENXIO; in radeon_find_mem_vbios()
533 rinfo->bios_seg = rom_base; in radeon_find_mem_vbios()
534 rinfo->fp_bios_start = BIOS_IN16(0x48); in radeon_find_mem_vbios()
543 * tree. Hopefully, ATI OF driver is kind enough to fill these
547 struct device_node *dp = rinfo->of_node; in radeon_read_xtal_OF()
551 return -ENODEV; in radeon_read_xtal_OF()
555 return -EINVAL; in radeon_read_xtal_OF()
558 rinfo->pll.ref_clk = (*val) / 10; in radeon_read_xtal_OF()
562 rinfo->pll.sclk = (*val) / 10; in radeon_read_xtal_OF()
566 rinfo->pll.mclk = (*val) / 10; in radeon_read_xtal_OF()
588 * here, so... --BenH in radeon_probe_pll_params()
616 return -1; in radeon_probe_pll_params()
685 return -1; in radeon_probe_pll_params()
698 rinfo->pll.ref_clk = xtal; in radeon_probe_pll_params()
699 rinfo->pll.ref_div = ref_div; in radeon_probe_pll_params()
700 rinfo->pll.sclk = sclk; in radeon_probe_pll_params()
701 rinfo->pll.mclk = mclk; in radeon_probe_pll_params()
716 switch (rinfo->chipset) { in radeon_get_pllinfo()
719 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
720 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
721 rinfo->pll.mclk = 23000; in radeon_get_pllinfo()
722 rinfo->pll.sclk = 23000; in radeon_get_pllinfo()
723 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
730 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
731 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
732 rinfo->pll.mclk = 27500; in radeon_get_pllinfo()
733 rinfo->pll.sclk = 27500; in radeon_get_pllinfo()
734 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
740 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
741 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
742 rinfo->pll.mclk = 25000; in radeon_get_pllinfo()
743 rinfo->pll.sclk = 25000; in radeon_get_pllinfo()
744 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
750 rinfo->pll.ppll_max = 40000; in radeon_get_pllinfo()
751 rinfo->pll.ppll_min = 20000; in radeon_get_pllinfo()
752 rinfo->pll.mclk = 27000; in radeon_get_pllinfo()
753 rinfo->pll.sclk = 27000; in radeon_get_pllinfo()
754 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
761 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
762 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
763 rinfo->pll.mclk = 16600; in radeon_get_pllinfo()
764 rinfo->pll.sclk = 16600; in radeon_get_pllinfo()
765 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
768 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()
785 if (!force_measure_pll && rinfo->bios_seg) { in radeon_get_pllinfo()
786 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); in radeon_get_pllinfo()
788 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); in radeon_get_pllinfo()
789 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); in radeon_get_pllinfo()
790 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); in radeon_get_pllinfo()
791 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); in radeon_get_pllinfo()
792 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); in radeon_get_pllinfo()
793 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); in radeon_get_pllinfo()
809 * Fall back to already-set defaults... in radeon_get_pllinfo()
819 if (rinfo->pll.mclk == 0) in radeon_get_pllinfo()
820 rinfo->pll.mclk = 20000; in radeon_get_pllinfo()
821 if (rinfo->pll.sclk == 0) in radeon_get_pllinfo()
822 rinfo->pll.sclk = 20000; in radeon_get_pllinfo()
825 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, in radeon_get_pllinfo()
826 rinfo->pll.ref_div, in radeon_get_pllinfo()
827 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, in radeon_get_pllinfo()
828 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); in radeon_get_pllinfo()
829 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); in radeon_get_pllinfo()
834 struct radeonfb_info *rinfo = info->par; in radeonfb_check_var()
840 return -EINVAL; in radeonfb_check_var()
853 return -EINVAL; in radeonfb_check_var()
904 var->xres, var->yres, var->bits_per_pixel); in radeonfb_check_var()
905 return -EINVAL; in radeonfb_check_var()
917 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) { in radeonfb_check_var()
925 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram) in radeonfb_check_var()
926 return -EINVAL; in radeonfb_check_var()
931 if (v.xoffset > v.xres_virtual - v.xres) in radeonfb_check_var()
932 v.xoffset = v.xres_virtual - v.xres - 1; in radeonfb_check_var()
934 if (v.yoffset > v.yres_virtual - v.yres) in radeonfb_check_var()
935 v.yoffset = v.yres_virtual - v.yres - 1; in radeonfb_check_var()
950 struct radeonfb_info *rinfo = info->par; in radeonfb_pan_display()
952 if ((var->xoffset + info->var.xres > info->var.xres_virtual) in radeonfb_pan_display()
953 || (var->yoffset + info->var.yres > info->var.yres_virtual)) in radeonfb_pan_display()
954 return -EINVAL; in radeonfb_pan_display()
956 if (rinfo->asleep) in radeonfb_pan_display()
960 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length + in radeonfb_pan_display()
961 var->xoffset * info->var.bits_per_pixel / 8) & ~7); in radeonfb_pan_display()
969 struct radeonfb_info *rinfo = info->par; in radeonfb_ioctl()
976 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's in radeonfb_ioctl()
981 if (!rinfo->is_mobility) in radeonfb_ioctl()
982 return -EINVAL; in radeonfb_ioctl()
1018 if (!rinfo->is_mobility) in radeonfb_ioctl()
1019 return -EINVAL; in radeonfb_ioctl()
1031 return -EINVAL; in radeonfb_ioctl()
1034 return -EINVAL; in radeonfb_ioctl()
1044 if (rinfo->lock_blank) in radeon_screen_blank()
1073 switch (rinfo->mon1_type) { in radeon_screen_blank()
1085 del_timer_sync(&rinfo->lvds_timer); in radeon_screen_blank()
1089 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl in radeon_screen_blank()
1096 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; in radeon_screen_blank()
1097 rinfo->init_state.lvds_gen_cntl |= in radeon_screen_blank()
1100 radeon_msleep(rinfo->panel_info.pwr_delay); in radeon_screen_blank()
1104 rinfo->pending_lvds_gen_cntl = target_val; in radeon_screen_blank()
1105 mod_timer(&rinfo->lvds_timer, in radeon_screen_blank()
1107 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); in radeon_screen_blank()
1114 /* We don't do a full switch-off on a simple mode switch */ in radeon_screen_blank()
1122 if (rinfo->is_mobility || rinfo->is_IGP) in radeon_screen_blank()
1130 rinfo->pending_lvds_gen_cntl = val; in radeon_screen_blank()
1131 mod_timer(&rinfo->lvds_timer, in radeon_screen_blank()
1133 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); in radeon_screen_blank()
1134 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; in radeon_screen_blank()
1135 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; in radeon_screen_blank()
1136 if (rinfo->is_mobility || rinfo->is_IGP) in radeon_screen_blank()
1151 struct radeonfb_info *rinfo = info->par; in radeonfb_blank()
1153 if (rinfo->asleep) in radeonfb_blank()
1168 return -EINVAL; in radeon_setcolreg()
1173 rinfo->palette[regno].red = red; in radeon_setcolreg()
1174 rinfo->palette[regno].green = green; in radeon_setcolreg()
1175 rinfo->palette[regno].blue = blue; in radeon_setcolreg()
1180 if (!rinfo->asleep) { in radeon_setcolreg()
1183 if (rinfo->bpp == 16) { in radeon_setcolreg()
1186 if (rinfo->depth == 16 && regno > 63) in radeon_setcolreg()
1187 return -EINVAL; in radeon_setcolreg()
1188 if (rinfo->depth == 15 && regno > 31) in radeon_setcolreg()
1189 return -EINVAL; in radeon_setcolreg()
1194 if (rinfo->depth == 16) { in radeon_setcolreg()
1197 (rinfo->palette[regno>>1].red << 16) | in radeon_setcolreg()
1199 (rinfo->palette[regno>>1].blue)); in radeon_setcolreg()
1200 green = rinfo->palette[regno<<1].green; in radeon_setcolreg()
1204 if (rinfo->depth != 16 || regno < 32) { in radeon_setcolreg()
1211 u32 *pal = rinfo->info->pseudo_palette; in radeon_setcolreg()
1212 switch (rinfo->depth) { in radeon_setcolreg()
1235 struct radeonfb_info *rinfo = info->par; in radeonfb_setcolreg()
1239 if (!rinfo->asleep) { in radeonfb_setcolreg()
1240 if (rinfo->is_mobility) { in radeonfb_setcolreg()
1247 if (rinfo->has_CRTC2) { in radeonfb_setcolreg()
1256 if (!rinfo->asleep && rinfo->is_mobility) in radeonfb_setcolreg()
1264 struct radeonfb_info *rinfo = info->par; in radeonfb_setcmap()
1269 if (!rinfo->asleep) { in radeonfb_setcmap()
1270 if (rinfo->is_mobility) { in radeonfb_setcmap()
1277 if (rinfo->has_CRTC2) { in radeonfb_setcmap()
1284 red = cmap->red; in radeonfb_setcmap()
1285 green = cmap->green; in radeonfb_setcmap()
1286 blue = cmap->blue; in radeonfb_setcmap()
1287 transp = cmap->transp; in radeonfb_setcmap()
1288 start = cmap->start; in radeonfb_setcmap()
1290 for (i = 0; i < cmap->len; i++) { in radeonfb_setcmap()
1304 if (!rinfo->asleep && rinfo->is_mobility) in radeonfb_setcmap()
1314 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); in radeon_save_state()
1315 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); in radeon_save_state()
1316 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); in radeon_save_state()
1317 save->dac_cntl = INREG(DAC_CNTL); in radeon_save_state()
1318 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); in radeon_save_state()
1319 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); in radeon_save_state()
1320 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); in radeon_save_state()
1321 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); in radeon_save_state()
1322 save->crtc_pitch = INREG(CRTC_PITCH); in radeon_save_state()
1323 save->surface_cntl = INREG(SURFACE_CNTL); in radeon_save_state()
1326 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); in radeon_save_state()
1327 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); in radeon_save_state()
1328 save->fp_gen_cntl = INREG(FP_GEN_CNTL); in radeon_save_state()
1329 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); in radeon_save_state()
1330 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); in radeon_save_state()
1331 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); in radeon_save_state()
1332 save->fp_vert_stretch = INREG(FP_VERT_STRETCH); in radeon_save_state()
1333 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); in radeon_save_state()
1334 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); in radeon_save_state()
1335 save->tmds_crc = INREG(TMDS_CRC); in radeon_save_state()
1336 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); in radeon_save_state()
1337 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); in radeon_save_state()
1340 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; in radeon_save_state()
1342 save->ppll_div_3 = INPLL(PPLL_DIV_3); in radeon_save_state()
1343 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()
1354 if (rinfo->is_mobility) { in radeon_write_pll_regs()
1362 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
1363 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
1369 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
1387 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
1394 rinfo->family == CHIP_FAMILY_RS300 || in radeon_write_pll_regs()
1395 rinfo->family == CHIP_FAMILY_RS400 || in radeon_write_pll_regs()
1396 rinfo->family == CHIP_FAMILY_RS480) { in radeon_write_pll_regs()
1397 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_write_pll_regs()
1401 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
1405 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_write_pll_regs()
1409 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
1412 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
1413 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
1450 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); in radeon_lvds_timer_func()
1475 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); in radeon_write_mode()
1476 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); in radeon_write_mode()
1477 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); in radeon_write_mode()
1480 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); in radeon_write_mode()
1481 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_write_mode()
1483 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); in radeon_write_mode()
1484 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); in radeon_write_mode()
1485 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); in radeon_write_mode()
1486 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); in radeon_write_mode()
1487 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); in radeon_write_mode()
1488 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); in radeon_write_mode()
1491 OUTREG(CRTC_PITCH, mode->crtc_pitch); in radeon_write_mode()
1492 OUTREG(SURFACE_CNTL, mode->surface_cntl); in radeon_write_mode()
1498 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); in radeon_write_mode()
1499 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); in radeon_write_mode()
1500 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); in radeon_write_mode()
1501 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); in radeon_write_mode()
1502 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); in radeon_write_mode()
1503 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); in radeon_write_mode()
1504 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); in radeon_write_mode()
1505 OUTREG(TMDS_CRC, mode->tmds_crc); in radeon_write_mode()
1506 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); in radeon_write_mode()
1513 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); in radeon_write_mode()
1556 while (rinfo->has_CRTC2) { in radeon_calc_pll_regs()
1567 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) { in radeon_calc_pll_regs()
1578 /* sourced from CRTC2 -> exit */ in radeon_calc_pll_regs()
1589 if (freq > rinfo->pll.ppll_max) in radeon_calc_pll_regs()
1590 freq = rinfo->pll.ppll_max; in radeon_calc_pll_regs()
1591 if (freq*12 < rinfo->pll.ppll_min) in radeon_calc_pll_regs()
1592 freq = rinfo->pll.ppll_min / 12; in radeon_calc_pll_regs()
1594 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); in radeon_calc_pll_regs()
1596 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs()
1597 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1601 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs()
1603 if (pll_output_freq >= rinfo->pll.ppll_min && in radeon_calc_pll_regs()
1604 pll_output_freq <= rinfo->pll.ppll_max) in radeon_calc_pll_regs()
1609 given by the terminal post_div->bitvalue */ in radeon_calc_pll_regs()
1610 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1611 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1612 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1615 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1619 given by the terminal post_div->bitvalue */ in radeon_calc_pll_regs()
1620 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1621 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1622 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1625 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1628 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1629 rinfo->pll.ref_clk); in radeon_calc_pll_regs()
1630 regs->ppll_ref_div = rinfo->pll.ref_div; in radeon_calc_pll_regs()
1631 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1633 pr_debug("post div = 0x%x\n", post_div->bitvalue); in radeon_calc_pll_regs()
1635 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); in radeon_calc_pll_regs()
1640 struct radeonfb_info *rinfo = info->par; in radeonfb_set_par()
1641 struct fb_var_screeninfo *mode = &info->var; in radeonfb_set_par()
1658 return -ENOMEM; in radeonfb_set_par()
1665 hSyncStart = mode->xres + mode->right_margin; in radeonfb_set_par()
1666 hSyncEnd = hSyncStart + mode->hsync_len; in radeonfb_set_par()
1667 hTotal = hSyncEnd + mode->left_margin; in radeonfb_set_par()
1669 vSyncStart = mode->yres + mode->lower_margin; in radeonfb_set_par()
1670 vSyncEnd = vSyncStart + mode->vsync_len; in radeonfb_set_par()
1671 vTotal = vSyncEnd + mode->upper_margin; in radeonfb_set_par()
1672 pixClock = mode->pixclock; in radeonfb_set_par()
1674 sync = mode->sync; in radeonfb_set_par()
1679 if (rinfo->panel_info.xres < mode->xres) in radeonfb_set_par()
1680 mode->xres = rinfo->panel_info.xres; in radeonfb_set_par()
1681 if (rinfo->panel_info.yres < mode->yres) in radeonfb_set_par()
1682 mode->yres = rinfo->panel_info.yres; in radeonfb_set_par()
1684 hTotal = mode->xres + rinfo->panel_info.hblank; in radeonfb_set_par()
1685 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; in radeonfb_set_par()
1686 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; in radeonfb_set_par()
1688 vTotal = mode->yres + rinfo->panel_info.vblank; in radeonfb_set_par()
1689 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; in radeonfb_set_par()
1690 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; in radeonfb_set_par()
1692 h_sync_pol = !rinfo->panel_info.hAct_high; in radeonfb_set_par()
1693 v_sync_pol = !rinfo->panel_info.vAct_high; in radeonfb_set_par()
1695 pixClock = 100000000 / rinfo->panel_info.clock; in radeonfb_set_par()
1697 if (rinfo->panel_info.use_bios_dividers) { in radeonfb_set_par()
1699 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | in radeonfb_set_par()
1700 (rinfo->panel_info.post_divider << 16); in radeonfb_set_par()
1701 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; in radeonfb_set_par()
1712 hsync_wid = (hSyncEnd - hSyncStart) / 8; in radeonfb_set_par()
1713 vsync_wid = vSyncEnd - vSyncStart; in radeonfb_set_par()
1727 hsync_fudge = hsync_fudge_fp[format-1]; in radeonfb_set_par()
1729 hsync_fudge = hsync_adj_tab[format-1]; in radeonfb_set_par()
1731 hsync_start = hSyncStart - 8 + hsync_fudge; in radeonfb_set_par()
1733 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | in radeonfb_set_par()
1736 /* Clear auto-center etc... */ in radeonfb_set_par()
1737 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; in radeonfb_set_par()
1738 newmode->crtc_more_cntl &= 0xfffffff0; in radeonfb_set_par()
1741 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; in radeonfb_set_par()
1743 newmode->crtc_ext_cntl |= CRTC_CRT_ON; in radeonfb_set_par()
1745 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | in radeonfb_set_par()
1748 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | in radeonfb_set_par()
1752 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | in radeonfb_set_par()
1755 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | in radeonfb_set_par()
1756 (((mode->xres / 8) - 1) << 16)); in radeonfb_set_par()
1758 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | in radeonfb_set_par()
1761 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | in radeonfb_set_par()
1762 ((mode->yres - 1) << 16); in radeonfb_set_par()
1764 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | in radeonfb_set_par()
1767 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { in radeonfb_set_par()
1769 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) in radeonfb_set_par()
1772 /* Then, re-multiply it to get the CRTC pitch */ in radeonfb_set_par()
1773 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); in radeonfb_set_par()
1775 newmode->crtc_pitch = (mode->xres_virtual >> 3); in radeonfb_set_par()
1777 newmode->crtc_pitch |= (newmode->crtc_pitch << 16); in radeonfb_set_par()
1784 newmode->surface_cntl = 0; in radeonfb_set_par()
1792 switch (mode->bits_per_pixel) { in radeonfb_set_par()
1794 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; in radeonfb_set_par()
1795 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; in radeonfb_set_par()
1799 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; in radeonfb_set_par()
1800 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; in radeonfb_set_par()
1807 newmode->surf_lower_bound[i] = 0; in radeonfb_set_par()
1808 newmode->surf_upper_bound[i] = 0x1f; in radeonfb_set_par()
1809 newmode->surf_info[i] = 0; in radeonfb_set_par()
1813 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid); in radeonfb_set_par()
1815 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid); in radeonfb_set_par()
1817 rinfo->bpp = mode->bits_per_pixel; in radeonfb_set_par()
1818 rinfo->depth = depth; in radeonfb_set_par()
1824 newmode->clk_cntl_index = 0x300; in radeonfb_set_par()
1830 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; in radeonfb_set_par()
1835 if (mode->xres > rinfo->panel_info.xres) in radeonfb_set_par()
1836 mode->xres = rinfo->panel_info.xres; in radeonfb_set_par()
1837 if (mode->yres > rinfo->panel_info.yres) in radeonfb_set_par()
1838 mode->yres = rinfo->panel_info.yres; in radeonfb_set_par()
1840 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) in radeonfb_set_par()
1842 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) in radeonfb_set_par()
1845 if (mode->xres != rinfo->panel_info.xres) { in radeonfb_set_par()
1846 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, in radeonfb_set_par()
1847 rinfo->panel_info.xres); in radeonfb_set_par()
1848 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) | in radeonfb_set_par()
1849 (newmode->fp_horz_stretch & in radeonfb_set_par()
1852 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | in radeonfb_set_par()
1856 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; in radeonfb_set_par()
1858 if (mode->yres != rinfo->panel_info.yres) { in radeonfb_set_par()
1859 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, in radeonfb_set_par()
1860 rinfo->panel_info.yres); in radeonfb_set_par()
1861 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) | in radeonfb_set_par()
1862 (newmode->fp_vert_stretch & in radeonfb_set_par()
1864 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | in radeonfb_set_par()
1868 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; in radeonfb_set_par()
1870 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32) in radeonfb_set_par()
1880 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | in radeonfb_set_par()
1885 (rinfo->family == CHIP_FAMILY_R200)) { in radeonfb_set_par()
1886 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; in radeonfb_set_par()
1888 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; in radeonfb_set_par()
1890 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; in radeonfb_set_par()
1892 newmode->fp_gen_cntl |= FP_SEL_CRTC1; in radeonfb_set_par()
1894 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; in radeonfb_set_par()
1895 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; in radeonfb_set_par()
1896 newmode->tmds_crc = rinfo->init_state.tmds_crc; in radeonfb_set_par()
1897 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; in radeonfb_set_par()
1900 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); in radeonfb_set_par()
1901 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); in radeonfb_set_par()
1904 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); in radeonfb_set_par()
1905 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); in radeonfb_set_par()
1908 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) in radeonfb_set_par()
1909 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; in radeonfb_set_par()
1911 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; in radeonfb_set_par()
1912 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; in radeonfb_set_par()
1915 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | in radeonfb_set_par()
1916 (((mode->xres / 8) - 1) << 16)); in radeonfb_set_par()
1917 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | in radeonfb_set_par()
1918 ((mode->yres - 1) << 16); in radeonfb_set_par()
1919 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | in radeonfb_set_par()
1921 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | in radeonfb_set_par()
1926 if (!rinfo->asleep) { in radeonfb_set_par()
1927 memcpy(&rinfo->state, newmode, sizeof(*newmode)); in radeonfb_set_par()
1930 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) in radeonfb_set_par()
1934 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) in radeonfb_set_par()
1935 info->fix.line_length = rinfo->pitch*64; in radeonfb_set_par()
1937 info->fix.line_length = mode->xres_virtual in radeonfb_set_par()
1938 * ((mode->bits_per_pixel + 1) / 8); in radeonfb_set_par()
1939 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR in radeonfb_set_par()
1944 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres, in radeonfb_set_par()
1945 rinfo->depth, info->fix.line_length); in radeonfb_set_par()
1973 struct fb_info *info = rinfo->info; in radeon_set_fbinfo()
1975 info->par = rinfo; in radeon_set_fbinfo()
1976 info->pseudo_palette = rinfo->pseudo_palette; in radeon_set_fbinfo()
1977 info->flags = FBINFO_HWACCEL_COPYAREA in radeon_set_fbinfo()
1981 info->fbops = &radeonfb_ops; in radeon_set_fbinfo()
1982 info->screen_base = rinfo->fb_base; in radeon_set_fbinfo()
1983 info->screen_size = rinfo->mapped_vram; in radeon_set_fbinfo()
1985 strscpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); in radeon_set_fbinfo()
1986 info->fix.smem_start = rinfo->fb_base_phys; in radeon_set_fbinfo()
1987 info->fix.smem_len = rinfo->video_ram; in radeon_set_fbinfo()
1988 info->fix.type = FB_TYPE_PACKED_PIXELS; in radeon_set_fbinfo()
1989 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in radeon_set_fbinfo()
1990 info->fix.xpanstep = 8; in radeon_set_fbinfo()
1991 info->fix.ypanstep = 1; in radeon_set_fbinfo()
1992 info->fix.ywrapstep = 0; in radeon_set_fbinfo()
1993 info->fix.type_aux = 0; in radeon_set_fbinfo()
1994 info->fix.mmio_start = rinfo->mmio_base_phys; in radeon_set_fbinfo()
1995 info->fix.mmio_len = RADEON_REGSIZE; in radeon_set_fbinfo()
1996 info->fix.accel = FB_ACCEL_ATI_RADEON; in radeon_set_fbinfo()
1998 fb_alloc_cmap(&info->cmap, 256, 0); in radeon_set_fbinfo()
2001 info->flags |= FBINFO_HWACCEL_DISABLED; in radeon_set_fbinfo()
2012 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
2027 if (rinfo->has_CRTC2) { in fixup_memory_mappings()
2044 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); in fixup_memory_mappings()
2045 rinfo->fb_local_base = aper_base; in fixup_memory_mappings()
2048 rinfo->fb_local_base = 0; in fixup_memory_mappings()
2069 if (rinfo->has_CRTC2) in fixup_memory_mappings()
2074 if (rinfo->has_CRTC2) in fixup_memory_mappings()
2083 if (rinfo->has_CRTC2) in fixup_memory_mappings()
2088 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), in fixup_memory_mappings()
2099 if ((rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2100 (rinfo->family == CHIP_FAMILY_RS200) || in radeon_identify_vram()
2101 (rinfo->family == CHIP_FAMILY_RS300) || in radeon_identify_vram()
2102 (rinfo->family == CHIP_FAMILY_RC410) || in radeon_identify_vram()
2103 (rinfo->family == CHIP_FAMILY_RS400) || in radeon_identify_vram()
2104 (rinfo->family == CHIP_FAMILY_RS480) ) { in radeon_identify_vram()
2107 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); in radeon_identify_vram()
2117 if ((rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2118 (rinfo->family == CHIP_FAMILY_RS200)) { in radeon_identify_vram()
2130 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK; in radeon_identify_vram()
2136 if (rinfo->video_ram == 0) { in radeon_identify_vram()
2137 switch (rinfo->pdev->device) { in radeon_identify_vram()
2140 rinfo->video_ram = 8192 * 1024; in radeon_identify_vram()
2151 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) || in radeon_identify_vram()
2153 rinfo->vram_ddr = 1; in radeon_identify_vram()
2155 rinfo->vram_ddr = 0; in radeon_identify_vram()
2161 case 0: rinfo->vram_width = 64; break; in radeon_identify_vram()
2162 case 1: rinfo->vram_width = 128; break; in radeon_identify_vram()
2163 case 2: rinfo->vram_width = 256; break; in radeon_identify_vram()
2164 default: rinfo->vram_width = 128; break; in radeon_identify_vram()
2166 } else if ((rinfo->family == CHIP_FAMILY_RV100) || in radeon_identify_vram()
2167 (rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2168 (rinfo->family == CHIP_FAMILY_RS200)){ in radeon_identify_vram()
2170 rinfo->vram_width = 32; in radeon_identify_vram()
2172 rinfo->vram_width = 64; in radeon_identify_vram()
2175 rinfo->vram_width = 128; in radeon_identify_vram()
2177 rinfo->vram_width = 64; in radeon_identify_vram()
2185 pci_name(rinfo->pdev), in radeon_identify_vram()
2186 rinfo->video_ram / 1024, in radeon_identify_vram()
2187 rinfo->vram_ddr ? "DDR" : "SDRAM", in radeon_identify_vram()
2188 rinfo->vram_width); in radeon_identify_vram()
2207 struct radeonfb_info *rinfo = info->par; in radeon_show_edid1()
2209 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID); in radeon_show_edid1()
2219 struct radeonfb_info *rinfo = info->par; in radeon_show_edid2()
2221 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID); in radeon_show_edid2()
2261 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev); in radeonfb_pci_register()
2263 ret = -ENOMEM; in radeonfb_pci_register()
2266 rinfo = info->par; in radeonfb_pci_register()
2267 rinfo->info = info; in radeonfb_pci_register()
2268 rinfo->pdev = pdev; in radeonfb_pci_register()
2270 spin_lock_init(&rinfo->reg_lock); in radeonfb_pci_register()
2271 timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0); in radeonfb_pci_register()
2273 c1 = ent->device >> 8; in radeonfb_pci_register()
2274 c2 = ent->device & 0xff; in radeonfb_pci_register()
2276 snprintf(rinfo->name, sizeof(rinfo->name), in radeonfb_pci_register()
2277 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2); in radeonfb_pci_register()
2279 snprintf(rinfo->name, sizeof(rinfo->name), in radeonfb_pci_register()
2280 "ATI Radeon %x", ent->device & 0xffff); in radeonfb_pci_register()
2282 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; in radeonfb_pci_register()
2283 rinfo->chipset = pdev->device; in radeonfb_pci_register()
2284 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; in radeonfb_pci_register()
2285 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; in radeonfb_pci_register()
2286 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; in radeonfb_pci_register()
2289 rinfo->fb_base_phys = pci_resource_start (pdev, 0); in radeonfb_pci_register()
2290 rinfo->mmio_base_phys = pci_resource_start (pdev, 2); in radeonfb_pci_register()
2300 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2307 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2312 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE); in radeonfb_pci_register()
2313 if (!rinfo->mmio_base) { in radeonfb_pci_register()
2315 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2316 ret = -EIO; in radeonfb_pci_register()
2320 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; in radeonfb_pci_register()
2325 rinfo->errata = 0; in radeonfb_pci_register()
2326 if (rinfo->family == CHIP_FAMILY_R300 && in radeonfb_pci_register()
2329 rinfo->errata |= CHIP_ERRATA_R300_CG; in radeonfb_pci_register()
2331 if (rinfo->family == CHIP_FAMILY_RV200 || in radeonfb_pci_register()
2332 rinfo->family == CHIP_FAMILY_RS200) in radeonfb_pci_register()
2333 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; in radeonfb_pci_register()
2335 if (rinfo->family == CHIP_FAMILY_RV100 || in radeonfb_pci_register()
2336 rinfo->family == CHIP_FAMILY_RS100 || in radeonfb_pci_register()
2337 rinfo->family == CHIP_FAMILY_RS200) in radeonfb_pci_register()
2338 rinfo->errata |= CHIP_ERRATA_PLL_DELAY; in radeonfb_pci_register()
2341 /* On PPC, we obtain the OF device-node pointer to the firmware in radeonfb_pci_register()
2344 rinfo->of_node = pci_device_to_OF_node(pdev); in radeonfb_pci_register()
2345 if (rinfo->of_node == NULL) in radeonfb_pci_register()
2347 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2361 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); in radeonfb_pci_register()
2364 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys, in radeonfb_pci_register()
2365 rinfo->mapped_vram); in radeonfb_pci_register()
2366 } while (rinfo->fb_base == NULL && in radeonfb_pci_register()
2367 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); in radeonfb_pci_register()
2369 if (rinfo->fb_base == NULL) { in radeonfb_pci_register()
2371 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2372 ret = -EIO; in radeonfb_pci_register()
2376 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev), in radeonfb_pci_register()
2377 rinfo->mapped_vram/1024); in radeonfb_pci_register()
2390 if (!rinfo->is_mobility) in radeonfb_pci_register()
2400 if (rinfo->bios_seg == NULL) in radeonfb_pci_register()
2407 if (rinfo->bios_seg == NULL && rinfo->is_mobility) in radeonfb_pci_register()
2428 if (rinfo->mon1_EDID) in radeonfb_pci_register()
2429 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, in radeonfb_pci_register()
2431 if (rinfo->mon2_EDID) in radeonfb_pci_register()
2432 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, in radeonfb_pci_register()
2441 radeon_save_state (rinfo, &rinfo->init_state); in radeonfb_pci_register()
2442 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); in radeonfb_pci_register()
2445 if (default_dynclk < -1) { in radeonfb_pci_register()
2446 /* -2 is special: means ON on mobility chips and do not in radeonfb_pci_register()
2449 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep); in radeonfb_pci_register()
2459 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2464 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys, in radeonfb_pci_register()
2465 rinfo->video_ram); in radeonfb_pci_register()
2470 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); in radeonfb_pci_register()
2472 if (rinfo->bios_seg) in radeonfb_pci_register()
2478 iounmap(rinfo->fb_base); in radeonfb_pci_register()
2480 kfree(rinfo->mon1_EDID); in radeonfb_pci_register()
2481 kfree(rinfo->mon2_EDID); in radeonfb_pci_register()
2482 if (rinfo->mon1_modedb) in radeonfb_pci_register()
2483 fb_destroy_modedb(rinfo->mon1_modedb); in radeonfb_pci_register()
2484 fb_dealloc_cmap(&info->cmap); in radeonfb_pci_register()
2488 if (rinfo->bios_seg) in radeonfb_pci_register()
2490 iounmap(rinfo->mmio_base); in radeonfb_pci_register()
2507 struct radeonfb_info *rinfo = info->par; in radeonfb_pci_unregister()
2514 if (rinfo->mon1_EDID) in radeonfb_pci_unregister()
2515 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); in radeonfb_pci_unregister()
2516 if (rinfo->mon2_EDID) in radeonfb_pci_unregister()
2517 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); in radeonfb_pci_unregister()
2519 del_timer_sync(&rinfo->lvds_timer); in radeonfb_pci_unregister()
2520 arch_phys_wc_del(rinfo->wc_cookie); in radeonfb_pci_unregister()
2524 iounmap(rinfo->mmio_base); in radeonfb_pci_unregister()
2525 iounmap(rinfo->fb_base); in radeonfb_pci_unregister()
2530 kfree(rinfo->mon1_EDID); in radeonfb_pci_unregister()
2531 kfree(rinfo->mon2_EDID); in radeonfb_pci_unregister()
2532 if (rinfo->mon1_modedb) in radeonfb_pci_unregister()
2533 fb_destroy_modedb(rinfo->mon1_modedb); in radeonfb_pci_unregister()
2537 fb_dealloc_cmap(&info->cmap); in radeonfb_pci_unregister()
2605 return -ENODEV; in radeonfb_init()
2609 return -ENODEV; in radeonfb_init()
2625 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2629 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2648 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");