21 #define MODE_QVGA	0
40 #define CMD0(x)		((0 << 30) | (x))
41 #define CMD1(x, x1)	((1 << 30) | ((x) << 9) | 0x100 | (x1))
42 #define CMD2(x, x1, x2)	((2 << 30) | ((x) << 18) | 0x20000 |\
43 			((x1) << 9) | 0x100 | (x2))
47 	CMD0(0x1), /* reset */
48 	CMD0(0x0), /* nop */
49 	CMD0(0x0), /* nop */
50 	CMD0(0x0), /* nop */
55 	CMD0(0x29),		/* Display ON */
56 	CMD2(0xB8, 0xFF, 0xF9),	/* Output Control */
57 	CMD0(0x11),		/* Sleep out */
58 	CMD1(0xB0, 0x16),	/* Wake */
63 	CMD0(0x28),		/* Display OFF */
64 	CMD2(0xB8, 0x80, 0x02),	/* Output Control */
65 	CMD0(0x10),		/* Sleep in */
66 	CMD1(0xB0, 0x00),	/* Deep stand by in */
71 	CMD1(0xB0, 0x16),
72 	CMD1(0xBC, 0x80),
73 	CMD1(0xE1, 0x00),
74 	CMD1(0x36, 0x50),
75 	CMD1(0x3B, 0x00),
80 	CMD1(0xB0, 0x16),
81 	CMD1(0xBC, 0x81),
82 	CMD1(0xE1, 0x00),
83 	CMD1(0x36, 0x50),
84 	CMD1(0x3B, 0x22),
89 	CMD1(0xcf, 0x02),	/* Blanking period control (1) */
90 	CMD2(0xd0, 0x08, 0x04),	/* Blanking period control (2) */
91 	CMD1(0xd1, 0x01),	/* CKV timing control on/off */
92 	CMD2(0xd2, 0x14, 0x00),	/* CKV 1,2 timing control */
93 	CMD2(0xd3, 0x1a, 0x0f),	/* OEV timing control */
94 	CMD2(0xd4, 0x1f, 0xaf),	/* ASW timing control (1) */
95 	CMD1(0xd5, 0x14),	/* ASW timing control (2) */
96 	CMD0(0x21),		/* Invert for normally black display */
97 	CMD0(0x29),		/* Display on */
102 	CMD1(0xd6, 0x02),	/* Blanking period control (1) */
103 	CMD2(0xd7, 0x08, 0x04),	/* Blanking period control (2) */
104 	CMD1(0xd8, 0x01),	/* CKV timing control on/off */
105 	CMD2(0xd9, 0x00, 0x08),	/* CKV 1,2 timing control */
106 	CMD2(0xde, 0x05, 0x0a),	/* OEV timing control */
107 	CMD2(0xdf, 0x0a, 0x19),	/* ASW timing control (1) */
108 	CMD1(0xe0, 0x0a),	/* ASW timing control (2) */
109 	CMD0(0x21),		/* Invert for normally black display */
110 	CMD0(0x29),		/* Display on */
115 	CMD1(0xB0, 0x16),
116 	CMD1(0xBC, 0x80),
117 	CMD1(0xE1, 0x00),
118 	CMD1(0x3B, 0x00),
123 	CMD1(0xB0, 0x16),
124 	CMD1(0xBC, 0x81),
125 	CMD1(0xE1, 0x00),
126 	CMD1(0x3B, 0x22),
131 	CMD1(0xcf, 0x02),	/* Blanking period control (1) */
132 	CMD2(0xd0, 0x08, 0x04),	/* Blanking period control (2) */
133 	CMD1(0xd1, 0x01),	/* CKV timing control on/off */
134 	CMD2(0xd2, 0x00, 0x1e),	/* CKV 1,2 timing control */
135 	CMD2(0xd3, 0x14, 0x28),	/* OEV timing control */
136 	CMD2(0xd4, 0x28, 0x64),	/* ASW timing control (1) */
137 	CMD1(0xd5, 0x28),	/* ASW timing control (2) */
138 	CMD0(0x21),		/* Invert for normally black display */
139 	CMD0(0x29),		/* Display on */
144 	CMD2(0xb8, 0xff, 0xf9),	/* Output control */
145 	CMD0(0x11),		/* sleep out */
146 	CMD1(0xba, 0x01),	/* Display mode (1) */
147 	CMD1(0xbb, 0x00),	/* Display mode (2) */
148 	CMD1(0x3a, 0x60),	/* Display mode 18-bit RGB */
149 	CMD1(0xbf, 0x10),	/* Drive system change control */
150 	CMD1(0xb1, 0x56),	/* Booster operation setup */
151 	CMD1(0xb2, 0x33),	/* Booster mode setup */
152 	CMD1(0xb3, 0x11),	/* Booster frequency setup */
153 	CMD1(0xb4, 0x02),	/* Op amp/system clock */
154 	CMD1(0xb5, 0x35),	/* VCS voltage */
155 	CMD1(0xb6, 0x40),	/* VCOM voltage */
156 	CMD1(0xb7, 0x03),	/* External display signal */
157 	CMD1(0xbd, 0x00),	/* ASW slew rate */
158 	CMD1(0xbe, 0x00),	/* Dummy data for QuadData operation */
159 	CMD1(0xc0, 0x11),	/* Sleep out FR count (A) */
160 	CMD1(0xc1, 0x11),	/* Sleep out FR count (B) */
161 	CMD1(0xc2, 0x11),	/* Sleep out FR count (C) */
162 	CMD2(0xc3, 0x20, 0x40),	/* Sleep out FR count (D) */
163 	CMD2(0xc4, 0x60, 0xc0),	/* Sleep out FR count (E) */
164 	CMD2(0xc5, 0x10, 0x20),	/* Sleep out FR count (F) */
165 	CMD1(0xc6, 0xc0),	/* Sleep out FR count (G) */
166 	CMD2(0xc7, 0x33, 0x43),	/* Gamma 1 fine tuning (1) */
167 	CMD1(0xc8, 0x44),	/* Gamma 1 fine tuning (2) */
168 	CMD1(0xc9, 0x33),	/* Gamma 1 inclination adjustment */
169 	CMD1(0xca, 0x00),	/* Gamma 1 blue offset adjustment */
170 	CMD2(0xec, 0x01, 0xf0),	/* Horizontal clock cycles */
179 	int nparams, err = 0;  in tdo24m_writes()
182 		if (!lcd->color_invert && *p == CMD0(0x21))  in tdo24m_writes()
185 		nparams = (*p >> 30) & 0x3;  in tdo24m_writes()
189 		case 0:  in tdo24m_writes()
190 			lcd->buf[0] = (data >> 8) & 0xff;  in tdo24m_writes()
191 			lcd->buf[1] = data & 0xff;  in tdo24m_writes()
194 			lcd->buf[0] = (data >> 16) & 0xff;  in tdo24m_writes()
195 			lcd->buf[1] = (data >> 8) & 0xff;  in tdo24m_writes()
196 			lcd->buf[2] = data & 0xff;  in tdo24m_writes()
199 			lcd->buf[0] = (data >> 24) & 0xff;  in tdo24m_writes()
200 			lcd->buf[1] = (data >> 16) & 0xff;  in tdo24m_writes()
201 			lcd->buf[2] = (data >> 8) & 0xff;  in tdo24m_writes()
202 			lcd->buf[3] = data & 0xff;  in tdo24m_writes()
234 	return 0;  in tdo24m_adj_mode()
255 	return 0;  in tdo35s_adj_mode()
282 	int ret = 0;  in tdo24m_power()
319 		return 0;  in tdo24m_set_mode()
368 	x->cs_change = 0;  in tdo24m_probe()
369 	x->tx_buf = &lcd->buf[0];  in tdo24m_probe()
379 		lcd->color_invert = 0;  in tdo24m_probe()
396 	return 0;  in tdo24m_probe()