Lines Matching +full:use +full:- +full:parity
1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
104 #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char)
107 #define LCR_PAR_NONE 0x00 // No parity
108 #define LCR_PAR_ODD 0x08 // Odd parity
109 #define LCR_PAR_EVEN 0x18 // Even parity
110 #define LCR_PAR_MARK 0x28 // Force parity bit to 1
111 #define LCR_PAR_SPACE 0x38 // Force parity bit to 0
112 #define LCR_PAR_MASK 0x38 // Mask for parity field
118 // and also the '654-only registers
134 #define LSR_PAR_ERR 0x04 // Rx parity error
144 #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1
154 //-------------------------------
188 #define EFR_AUTO_RTS 0x40 // Use RTS for Rx flow control
189 #define EFR_AUTO_CTS 0x80 // Use CTS for Tx flow control