Lines Matching defs:usb_dr_mmap
289 struct usb_dr_mmap { struct
291 u8 res1[256];
292 u16 caplength; /* Capability Register Length */
293 u16 hciversion; /* Host Controller Interface Version */
294 u32 hcsparams; /* Host Controller Structual Parameters */
295 u32 hccparams; /* Host Controller Capability Parameters */
296 u8 res2[20];
297 u32 dciversion; /* Device Controller Interface Version */
298 u32 dccparams; /* Device Controller Capability Parameters */
299 u8 res3[24];
301 u32 usbcmd; /* USB Command Register */
302 u32 usbsts; /* USB Status Register */
303 u32 usbintr; /* USB Interrupt Enable Register */
304 u32 frindex; /* Frame Index Register */
305 u8 res4[4];
306 u32 deviceaddr; /* Device Address */
307 u32 endpointlistaddr; /* Endpoint List Address Register */
308 u8 res5[4];
309 u32 burstsize; /* Master Interface Data Burst Size Register */
310 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
311 u8 res6[8];
312 u32 ulpiview; /* ULPI register access */
313 u8 res7[12];
314 u32 configflag; /* Configure Flag Register */
315 u32 portsc; /* Port 1 Status and Control Register */
316 u8 res8[28];
317 u32 otgsc; /* On-The-Go Status and Control */
318 u32 usbmode; /* USB Mode Register */
319 u32 endptsetupstat; /* Endpoint Setup Status Register */
320 u32 endpointprime; /* Endpoint Initialization Register */
321 u32 endptflush; /* Endpoint Flush Register */
322 u32 endptstatus; /* Endpoint Status Register */
323 u32 endptcomplete; /* Endpoint Complete Register */
324 u32 endptctrl[6]; /* Endpoint Control Registers */
325 u8 res9[552];
326 u32 snoop1;
327 u32 snoop2;
328 u32 age_cnt_thresh; /* Age Count Threshold Register */
329 u32 pri_ctrl; /* Priority Control Register */
330 u32 si_ctrl; /* System Interface Control Register */
331 u8 res10[236];
332 u32 control; /* General Purpose Control Register */