1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include	"xhci-ext-caps.h"
24 #include "pci-quirks.h"
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
35 /* Max number of USB devices for any host controller - limit in section 6.1 */
55  * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
57  * @hcs_params1:	HCSPARAMS1 - Structural Parameters 1
58  * @hcs_params2:	HCSPARAMS2 - Structural Parameters 2
59  * @hcs_params3:	HCSPARAMS3 - Structural Parameters 3
60  * @hcc_params:		HCCPARAMS - Capability Parameters
61  * @db_off:		DBOFF - Doorbell array offset
62  * @run_regs_off:	RTSOFF - Runtime register space offset
74 	/* Reserved up to (CAPLENGTH - 0x1C) */
78  * struct xhci_port_regs - Host Controller USB Port Register Set. xHCI spec 5.4.8
82  * @porthlmpc:	Port Hardware LPM Control
92  * struct xhci_op_regs - xHCI Host Controller Operational Registers.
93  * @command:		USBCMD - xHC command register
94  * @status:		USBSTS - xHC status register
99  * @cmd_ring:		CRP - 64-bit Command Ring Pointer
100  * @dcbaa_ptr:		DCBAAP - 64-bit Device Context Base Address Array Pointer
101  * @config_reg:		CONFIG - Configure Register
112 	/* rsvd: offset 0x20-2F */
116 	/* rsvd: offset 0x3C-3FF */
121 /* USBCMD - USB command - command bitmasks */
122 /* start/stop HC execution - do not write unless HC is halted*/
124 /* Reset HC - resets internal HC state machine and all registers (except
129 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
131 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
134 /* light reset (port status stays unchanged) - reset completed when this is 0 */
139 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
141 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
142  * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
144  * disabled, or powered-off state.
154 /* USBSTS - USB status - status bitmasks */
155 /* HC not running - set to 1 when run/stop bit is cleared. */
159 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
164 /* save state status - '1' means xHC is saving state */
166 /* restore state status - '1' means xHC is restoring state */
172 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
177  * DNCTRL - Device Notification Control Register - dev_notification bitmasks
187 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
188 /* bit 0 - Cycle bit indicates the ownership of the command ring */
192 /* stop ring immediately - abort the currently executing command */
196 /* bits 63:6 - Command Ring pointer */
199 /* CONFIG - Configure Register - config_reg bitmasks */
200 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
206 /* bits 10:31 - reserved and should be preserved */
208 /* bits 15:0 - HCD page shift bit */
212  * struct xhci_intr_reg - Interrupt Register Set, v1.2 section 5.5.2.
213  * @iman:		IMAN - Interrupt Management Register. Used to enable
215  * @imod:		IMOD - Interrupt Moderation Register. Used to throttle interrupts.
216  * @erst_size:		ERSTSZ - Number of segments in the Event Ring Segment Table (ERST).
217  * @erst_base:		ERSTBA - Event ring segment table base address.
218  * @erst_dequeue:	ERDP - Event ring dequeue pointer.
220  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
237 /* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */
239 /* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */
244  * bits 15:0 - Interrupt Moderation Interval, the minimum interval between interrupts
249 /* bits 31:16 - Interrupt Moderation Counter, used to count down the time to the next interrupt */
253 /* bits 15:0 - Event Ring Segment Table Size, number of ERST entries */
257 /* bits 63:6 - Event Ring Segment Table Base Address Register */
262  * bits 2:0 - Dequeue ERST Segment Index (DESI), is the segment number (or alias) where the
267  * bit 3 - Event Handler Busy (EHB), whether the event ring is scheduled to be serviced by
271 /* bits 63:4 - Event Ring Dequeue Pointer */
277  * 		MFINDEX - current microframe number
292  * Bits  0 -  7: Endpoint target
293  * Bits  8 - 15: RsvdZ
294  * Bits 16 - 31: Stream ID
338  * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
339  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
352 /* Route String - 0:19 */
354 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
358 /* Is this LS/FS device connected through a HS hub? - bit 25 */
360 /* Set if the device is a hub - bit 26 */
362 /* Index of the last valid endpoint context in this device context - 27:31 */
365 #define LAST_CTX_TO_EP_NUM(p)	(((p) >> 27) - 1)
370 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
381  * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
383  * this low or full-speed device.  '0' if attached to root hub port.
387  * The number of the downstream facing port of the high-speed hub
395 /* USB device address - assigned by the HC */
414  * @deq:	64-bit ring dequeue pointer address.  If the endpoint only
422  * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
423  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
431 	/* offset 0x14 - 0x1f reserved for HC internal use */
437  * Endpoint State - bits 0:2
438  * 0 - disabled
439  * 1 - running
440  * 2 - halted due to halt condition - ok to manipulate endpoint ring
441  * 3 - stopped
442  * 4 - TRB error
443  * 5-7 - reserved
451 #define GET_EP_CTX_STATE(ctx)	(le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
453 /* Mult - Max number of burtst within an interval, in EP companion desc. */
458 /* Interval - period between requests to an endpoint - 125u increments. */
472  * Force Event - generate transfer events for all TRBs for this endpoint
487 /* bit 7 is Host Initiate Disable - for disabling stream selection */
502 /* bits 63:4 - TR Dequeue Pointer */
510  * @drop_context:	set the bit of the endpoint context you want to disable
520 	(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
522 	(le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
525  * It's useful to pre-allocate these for commands that cannot fail due to
526  * out-of-memory errors, like freeing streams.
550 	/* 64-bit stream ring address, cycle state, and stream type */
552 	/* offset 0x14 - 0x1f reserved for HC internal use */
556 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
594  * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
598 	/* ep_interval is zero-based */
600 	/* mult and num_packets are one-based */
647 /* Percentage of bus bandwidth reserved for non-periodic transfers */
676 	/* ----  Related to URB cancellation ---- */
794  * @dev_context_ptr	array of 64-bit DMA addresses for device contexts
797 	/* 64-bit device addresses; we only write 32-bit addresses */
809 	/* 64-bit buffer address, or immediate data */
820 #define TRB_TO_EP_ID(p)		(((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */
823 #define TRB_TO_EP_INDEX(p)	(TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */
829 /* Completion Code - only applicable for some types of TRBs */
927 		return "Stopped - Length Invalid";  in xhci_trb_comp_code_string()
929 		return "Stopped - Short Packet";  in xhci_trb_comp_code_string()
950 	/* 64-bit segment pointer*/
970 /* Address device - disable SetAddress */
973 /* Configure Endpoint - Deconfigure */
976 /* Stop Ring - Transfer State Preserve */
1009 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1023 /* Port ID - bits 31:24 */
1029 /* transfer_len bitmasks - bits 0:16 */
1036 /* Interrupter Target - which MSI-X vector to target the completion event at */
1040 /* Cycle bit - indicates TRB ownership by HC or HCD */
1112 /* Transfer Ring No-op (not for the command ring) */
1117 /* Disable Slot Command */
1141 /* Force Header Command - generate a transaction or link management packet */
1143 /* No-op Command - not for transfer rings */
1145 /* TRB IDs 24-31 reserved */
1159 /* Device Notification Event - device sent function wake notification */
1161 /* MFINDEX Wrap Event - microframe counter wrapped */
1163 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1165 /* Nec vendor-specific command completion event. */
1188 		return "No-Op";  in xhci_trb_type_string()
1192 		return "Disable Slot Command";  in xhci_trb_type_string()
1218 		return "No-Op Command";  in xhci_trb_type_string()
1245 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1256  * since the command ring is 64-byte aligned.
1261 #define MAX_RSVD_CMD_TRBS	(TRBS_PER_SEGMENT - 3)
1268 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr)	(TRB_MAX_BUFF_SIZE - \
1269 					(addr & (TRB_MAX_BUFF_SIZE - 1)))
1279 	for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL))
1287 	/* Max packet sized bounce buffer for td-fragmant alignment */
1386 	/* 64-bit event ring segment address */
1396 	/* xhci->event_ring keeps track of segment dma addresses */
1427 /* Use for lpm */
1438 	/* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1510 	/* Cached register copies of read-only HC data */
1526 	/* MSI-X/MSI vectors */
1569 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1572  * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1575  * they see this status (any time they drop and re-acquire xhci->lock).
1596  * commands, reset device commands, disable slot commands, and address device
1620 /* For controller with a broken Port Disable implementation */
1653 	/* support xHCI 1.0 spec USB2 hardware LPM */
1674 	/* platform-specific data -- must come last */
1705 		primary_hcd = hcd->primary_hcd;  in hcd_to_xhci()
1707 	return (struct xhci_hcd *) (primary_hcd->hcd_priv);  in hcd_to_xhci()
1712 	return xhci->main_hcd;  in xhci_to_hcd()
1717 	if (xhci->shared_hcd)  in xhci_get_usb3_hcd()
1718 		return xhci->shared_hcd;  in xhci_get_usb3_hcd()
1720 	if (!xhci->usb2_rhub.num_ports)  in xhci_get_usb3_hcd()
1721 		return xhci->main_hcd;  in xhci_get_usb3_hcd()
1735 	return xhci->allow_single_roothub &&  in xhci_has_one_roothub()
1736 	       (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);  in xhci_has_one_roothub()
1740 	dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1742 	dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1744 	dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1746 	dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1751  * Some xHCI implementations may support 64-bit address pointers.  Registers
1752  * with 64-bit address pointers should be written to with dword accesses by
1754  * xHCI implementations that do not support 64-bit address pointers will ignore
1781 	return (xhci->quirks & XHCI_LINK_TRB_QUIRK) ||  in xhci_link_chain_quirk()
1782 	       (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST)));  in xhci_link_chain_quirk()
2005 	return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,  in xhci_urb_to_transfer_ring()
2006 					xhci_get_endpoint_index(&urb->ep->desc),  in xhci_urb_to_transfer_ring()
2007 					urb->stream_id);  in xhci_urb_to_transfer_ring()
2017 	if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&  in xhci_urb_suitable_for_idt()
2018 	    usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&  in xhci_urb_suitable_for_idt()
2019 	    urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&  in xhci_urb_suitable_for_idt()
2020 	    !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&  in xhci_urb_suitable_for_idt()
2021 	    !urb->num_sgs)  in xhci_urb_suitable_for_idt()
2270 			"type '%s' -> raw %08x %08x %08x %08x",  in xhci_decode_trb()
2325 				s = "full-speed";  in xhci_decode_slot_context()
2328 				s = "low-speed";  in xhci_decode_slot_context()
2331 				s = "high-speed";  in xhci_decode_slot_context()
2334 				s = "super-speed";  in xhci_decode_slot_context()
2337 				s = "super-speed plus";  in xhci_decode_slot_context()
2342 			mtt ? " multi-TT" : "",  in xhci_decode_slot_context()
2406 	/* RO/ROS: Read-only */  in xhci_decode_portsc()
2410 		ret += sprintf(str + ret, "OCA "); /* No set for USB2 ports */  in xhci_decode_portsc()
2434 		ret += sprintf(str + ret, "WPR "); /* RsvdZ for USB2 ports */  in xhci_decode_portsc()
2444 		ret += sprintf(str + ret, "WRC "); /* RsvdZ for USB2 ports */  in xhci_decode_portsc()
2452 		ret += sprintf(str + ret, "CEC "); /* RsvdZ for USB2 ports */  in xhci_decode_portsc()