1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include	"xhci-ext-caps.h"
24 #include "pci-quirks.h"
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
35 /* Max number of USB devices for any host controller - limit in section 6.1 */
37 /* Section 5.3.3 - MaxPorts */
47  * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
49  * @hcs_params1:	HCSPARAMS1 - Structural Parameters 1
50  * @hcs_params2:	HCSPARAMS2 - Structural Parameters 2
51  * @hcs_params3:	HCSPARAMS3 - Structural Parameters 3
52  * @hcc_params:		HCCPARAMS - Capability Parameters
53  * @db_off:		DBOFF - Doorbell array offset
54  * @run_regs_off:	RTSOFF - Runtime register space offset
66 	/* Reserved up to (CAPLENGTH - 0x1C) */
78  * struct xhci_op_regs - xHCI Host Controller Operational Registers.
79  * @command:		USBCMD - xHC command register
80  * @status:		USBSTS - xHC status register
85  * @cmd_ring:		CRP - 64-bit Command Ring Pointer
86  * @dcbaa_ptr:		DCBAAP - 64-bit Device Context Base Address Array Pointer
87  * @config_reg:		CONFIG - Configure Register
88  * @port_status_base:	PORTSCn - base address for Port Status and Control
93  * @port_power_base:	PORTPMSCn - base address for
95  * @port_link_base:	PORTLIn - base address for Port Link Info (current
107 	/* rsvd: offset 0x20-2F */
111 	/* rsvd: offset 0x3C-3FF */
118 	/* registers for ports 2-255 */
122 /* USBCMD - USB command - command bitmasks */
123 /* start/stop HC execution - do not write unless HC is halted*/
125 /* Reset HC - resets internal HC state machine and all registers (except
130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
135 /* light reset (port status stays unchanged) - reset completed when this is 0 */
140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
143  * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
145  * disabled, or powered-off state.
155 /* IMAN - Interrupt Management Register */
159 /* USBSTS - USB status - status bitmasks */
160 /* HC not running - set to 1 when run/stop bit is cleared. */
162 /* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
164 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
169 /* save state status - '1' means xHC is saving state */
171 /* restore state status - '1' means xHC is restoring state */
177 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
182  * DNCTRL - Device Notification Control Register - dev_notification bitmasks
193 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
197 /* stop ring immediately - abort the currently executing command */
202 /* Command Ring pointer - bit mask for the lower 32 bits. */
205 /* CONFIG - Configure Register - config_reg bitmasks */
206 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
212 /* bits 10:31 - reserved and should be preserved */
215  * struct xhci_intr_reg - Interrupt Register Set
216  * @irq_pending:	IMAN - Interrupt Management Register.  Used to enable
218  * @irq_control:	IMOD - Interrupt Moderation Register.
224  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
243 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
254 /* Counter used to count down the time to the next interrupt - HW use only */
265 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
269 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
278  * 		MFINDEX - current microframe number
293  * Bits  0 -  7: Endpoint target
294  * Bits  8 - 15: RsvdZ
295  * Bits 16 - 31: Stream ID
339  * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
340  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
353 /* Route String - 0:19 */
355 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
359 /* Is this LS/FS device connected through a HS hub? - bit 25 */
361 /* Set if the device is a hub - bit 26 */
363 /* Index of the last valid endpoint context in this device context - 27:31 */
366 #define LAST_CTX_TO_EP_NUM(p)	(((p) >> 27) - 1)
371 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
382  * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
384  * this low or full-speed device.  '0' if attached to root hub port.
388  * The number of the downstream facing port of the high-speed hub
396 /* USB device address - assigned by the HC */
415  * @deq:	64-bit ring dequeue pointer address.  If the endpoint only
423  * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
424  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
432 	/* offset 0x14 - 0x1f reserved for HC internal use */
438  * Endpoint State - bits 0:2
439  * 0 - disabled
440  * 1 - running
441  * 2 - halted due to halt condition - ok to manipulate endpoint ring
442  * 3 - stopped
443  * 4 - TRB error
444  * 5-7 - reserved
452 #define GET_EP_CTX_STATE(ctx)	(le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
454 /* Mult - Max number of burtst within an interval, in EP companion desc. */
459 /* Interval - period between requests to an endpoint - 125u increments. */
473  * Force Event - generate transfer events for all TRBs for this endpoint
488 /* bit 7 is Host Initiate Disable - for disabling stream selection */
520 	(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
522 	(le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
525  * It's useful to pre-allocate these for commands that cannot fail due to
526  * out-of-memory errors, like freeing streams.
549 	/* 64-bit stream ring address, cycle state, and stream type */
551 	/* offset 0x14 - 0x1f reserved for HC internal use */
555 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
592  * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
596 	/* ep_interval is zero-based */
598 	/* mult and num_packets are one-based */
645 /* Percentage of bus bandwidth reserved for non-periodic transfers */
674 	/* ----  Related to URB cancellation ---- */
788  * @dev_context_ptr	array of 64-bit DMA addresses for device contexts
791 	/* 64-bit device addresses; we only write 32-bit addresses */
796 /* TODO: write function to set the 64-bit device DMA address */
804 	/* 64-bit buffer address, or immediate data */
815 #define TRB_TO_EP_ID(p)		(((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */
818 #define TRB_TO_EP_INDEX(p)	(TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */
824 /* Completion Code - only applicable for some types of TRBs */
855 #define COMP_STOPPED_SHORT_PACKET		28
922 		return "Stopped - Length Invalid";  in xhci_trb_comp_code_string()
924 		return "Stopped - Short Packet";  in xhci_trb_comp_code_string()
945 	/* 64-bit segment pointer*/
962 /* Address device - disable SetAddress */
965 /* Configure Endpoint - Deconfigure */
968 /* Stop Ring - Transfer State Preserve */
998 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1012 /* Port ID - bits 31:24 */
1018 /* transfer_len bitmasks - bits 0:16 */
1025 /* Interrupter Target - which MSI-X vector to target the completion event at */
1029 /* Cycle bit - indicates TRB ownership by HC or HCD */
1101 /* Transfer Ring No-op (not for the command ring) */
1130 /* Force Header Command - generate a transaction or link management packet */
1132 /* No-op Command - not for transfer rings */
1134 /* TRB IDs 24-31 reserved */
1148 /* Device Notification Event - device sent function wake notification */
1150 /* MFINDEX Wrap Event - microframe counter wrapped */
1152 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1154 /* Nec vendor-specific command completion event. */
1177 		return "No-Op";  in xhci_trb_type_string()
1207 		return "No-Op Command";  in xhci_trb_type_string()
1234 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1245  * since the command ring is 64-byte aligned.
1250 #define MAX_RSVD_CMD_TRBS	(TRBS_PER_SEGMENT - 3)
1257 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr)	(TRB_MAX_BUFF_SIZE - \
1258 					(addr & (TRB_MAX_BUFF_SIZE - 1)))
1268 	for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL))
1276 	/* Max packet sized bounce buffer for td-fragmant alignment */
1375 	/* 64-bit event ring segment address */
1385 	/* xhci->event_ring keeps track of segment dma addresses */
1427 	/* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1451  * Intel Lynx Point LP xHCI host.
1499 	/* Cached register copies of read-only HC data */
1517 	/* MSI-X/MSI vectors */
1559 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1562  * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1565  * they see this status (any time they drop and re-acquire xhci->lock).
1614 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL	BIT_ULL(28)
1663 	/* platform-specific data -- must come last */
1694 		primary_hcd = hcd->primary_hcd;  in hcd_to_xhci()
1696 	return (struct xhci_hcd *) (primary_hcd->hcd_priv);  in hcd_to_xhci()
1701 	return xhci->main_hcd;  in xhci_to_hcd()
1706 	if (xhci->shared_hcd)  in xhci_get_usb3_hcd()
1707 		return xhci->shared_hcd;  in xhci_get_usb3_hcd()
1709 	if (!xhci->usb2_rhub.num_ports)  in xhci_get_usb3_hcd()
1710 		return xhci->main_hcd;  in xhci_get_usb3_hcd()
1724 	return xhci->allow_single_roothub &&  in xhci_has_one_roothub()
1725 	       (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);  in xhci_has_one_roothub()
1729 	dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1731 	dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1733 	dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1735 	dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1740  * Some xHCI implementations may support 64-bit address pointers.  Registers
1741  * with 64-bit address pointers should be written to with dword accesses by
1743  * xHCI implementations that do not support 64-bit address pointers will ignore
1761 	return (xhci->quirks & XHCI_LINK_TRB_QUIRK) ||  in xhci_link_chain_quirk()
1762 	       (type == TYPE_ISOC && (xhci->quirks & XHCI_AMD_0x96_HOST));  in xhci_link_chain_quirk()
1966 	return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,  in xhci_urb_to_transfer_ring()
1967 					xhci_get_endpoint_index(&urb->ep->desc),  in xhci_urb_to_transfer_ring()
1968 					urb->stream_id);  in xhci_urb_to_transfer_ring()
1978 	if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&  in xhci_urb_suitable_for_idt()
1979 	    usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&  in xhci_urb_suitable_for_idt()
1980 	    urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&  in xhci_urb_suitable_for_idt()
1981 	    !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&  in xhci_urb_suitable_for_idt()
1982 	    !urb->num_sgs)  in xhci_urb_suitable_for_idt()
2231 			"type '%s' -> raw %08x %08x %08x %08x",  in xhci_decode_trb()
2286 				s = "full-speed";  in xhci_decode_slot_context()
2289 				s = "low-speed";  in xhci_decode_slot_context()
2292 				s = "high-speed";  in xhci_decode_slot_context()
2295 				s = "super-speed";  in xhci_decode_slot_context()
2298 				s = "super-speed plus";  in xhci_decode_slot_context()
2303 			mtt ? " multi-TT" : "",  in xhci_decode_slot_context()
2365 		      portsc & PORT_POWER	? "Powered" : "Powered-off",  in xhci_decode_portsc()
2366 		      portsc & PORT_CONNECT	? "Connected" : "Not-connected",  in xhci_decode_portsc()
2374 		ret += sprintf(str + ret, "In-Reset ");  in xhci_decode_portsc()