Lines Matching +full:in +full:- +full:application
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * License. See the file "COPYING" in the main directory of this archive
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
14 * Redistribution and use in source and binary forms, with or without
21 * * Redistributions in binary form must reproduce the above
23 * disclaimer in the documentation and/or other materials provided
33 * regulations, and may be subject to export or import regulations in other
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
107 * core. In general, software need not know about this interface except to
110 * The application must program this register as part of the O2P USB core
119 * Indicates when the Periodic TxFIFO Empty Interrupt bit in the
121 * bit is used only in Slave mode.
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
130 * This bit is used only in Slave mode.
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
136 * * 1'b0: Core operates in Slave mode
137 * * 1'b1: Core operates in a DMA mode
142 * The application uses this bit to mask or unmask the interrupt
145 * * 1'b0: Mask the interrupt assertion to the application.
146 * * 1'b1: Unmask the interrupt assertion to the application.
172 * This value is in terms of 32-bit words.
181 * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType)
182 * * 1'b0: Asynchronous reset is used in the core
183 * * 1'b1: Synchronous reset is used in the core
195 * The application uses this bit to indicate the O2P USB core's
211 * - ...
236 * application. When an interrupt bit is masked, the interrupt associated with
258 * @incompisoinmsk: Incomplete Isochronous IN Transfer Mask
261 * @inepintmsk: IN Endpoints Interrupt Mask (INEPIntMsk)
274 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask
276 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk)
277 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk)
324 * This register interrupts the application for system-level events in the
325 * current mode of operation (Device mode or Host mode). It is shown in
326 * Interrupt. Some of the bits in this register are valid only in Host mode,
327 * while others are valid in Device mode only. This register also indicates the
328 * current mode of operation. In order to clear the interrupt status bits of
329 * type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status
339 * In Device mode, this interrupt is asserted when a resume is
340 * detected on the USB. In Host mode, this interrupt is asserted
343 * Power-Down and Clock Gating Programming Model" on
347 * In Host mode, this interrupt is asserted when a session request
348 * is detected from the device. In Device mode, this interrupt is
351 * Power-Down and Clock Gating Programming Model" on
356 * The core sets this bit when there is a change in connector ID
361 * written in the Periodic Request Queue. The half or completely
363 * bit in the Core AHB Configuration register
367 * on one of the channels of the core (in Host mode). The
368 * application must read the Host All Channels Interrupt (HAINT)
371 * Channel-n Interrupt (HCINTn) register to determine the exact
372 * cause of the interrupt. The application must clear the
373 * appropriate status bit in the HCINTn register to clear this bit.
375 * The core sets this bit to indicate a change in port status of
376 * one of the O2P USB core ports in Host mode. The application must
379 * application must clear the appropriate status bit in the Host
382 * This interrupt is valid only in DMA mode. This interrupt
383 * indicates that the core has stopped fetching data for IN
385 * Queue space. This interrupt is used by the application for an
388 * In Host mode, the core sets this interrupt bit when there are
394 * transfer is not completed in the current microframe. This
396 * Interrupt (EOPF) bit in this register.
397 * @incompisoin: Incomplete Isochronous IN Transfer (incompISOIN)
399 * one isochronous IN endpoint on which the transfer is not
400 * completed in the current microframe. This interrupt is asserted
401 * along with the End of Periodic Frame Interrupt (EOPF) bit in
405 * on one of the OUT endpoints of the core (in Device mode). The
406 * application must read the Device All Endpoints Interrupt
409 * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
411 * application must clear the appropriate status bit in the
413 * @iepint: IN Endpoints Interrupt (IEPInt)
415 * on one of the IN endpoints of the core (in Device mode). The
416 * application must read the Device All Endpoints Interrupt
417 * (DAINT) register to determine the exact number of the IN
419 * corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
421 * application must clear the appropriate status bit in the
424 * Indicates that an IN token has been received for a non-periodic
425 * endpoint, but the data for another endpoint is present in the
426 * top of the Non-Periodic Transmit FIFO and the IN endpoint
427 * mismatch count programmed by the application has expired.
429 * Indicates that the period specified in the Periodic Frame
431 * (DCFG.PerFrInt) has been reached in the current microframe.
439 * complete. The application must read the Device Status (DSTS)
457 * Indicates that the Set Global OUT NAK bit in the Device Control
458 * register (DCTL.SGOUTNak), set by the application, has taken
459 * effect in the core. This bit can be cleared by writing the Clear
460 * Global OUT NAK bit in the Device Control register
462 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff)
463 * Indicates that the Set Global Non-Periodic IN NAK bit in the
465 * application, has taken effect in the core. That is, the core has
466 * sampled the Global IN NAK bit set by the application. This bit
467 * can be cleared by clearing the Clear Global Non-Periodic IN
468 * NAK bit in the Device Control register (DCTL.CGNPInNak).
472 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp)
473 * This interrupt is asserted when the Non-Periodic TxFIFO is
475 * one entry to be written to the Non-Periodic Transmit Request
477 * the Non-Periodic TxFIFO Empty Level bit in the Core AHB
479 * @rxflvl: RxFIFO Non-Empty (RxFLvl)
483 * In Host mode, the core sets this bit to indicate that an SOF
484 * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
485 * USB. The application must write a 1 to this bit to clear the
487 * In Device mode, in the core sets this bit to indicate that an
488 * SOF token has been received on the USB. The application can read
494 * application must read the OTG Interrupt Status (GOTGINT)
496 * interrupt. The application must clear the appropriate status bit
497 * in the GOTGINT register to clear this bit.
499 * The core sets this bit when the application is trying to access:
500 * * A Host mode register, when the core is operating in Device
502 * * A Device mode register, when the core is operating in Host
552 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
554 * The application can program the RAM size and the memory start address for the
555 * Non-Periodic TxFIFO.
561 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep)
562 * This value is in terms of 32-bit words.
565 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
566 * This field contains the memory start address for Non-Periodic
579 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
581 * This read-only register contains the free space information for the
582 * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue.
588 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
589 * Entry in the Non-Periodic Tx Request Queue that is currently
593 * - 2'b00: IN/OUT token
594 * - 2'b01: Zero-length transmit packet (device IN/host OUT)
595 * - 2'b10: PING/CSPLIT token
596 * - 2'b11: Channel halt command
598 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available
600 * Indicates the amount of free space available in the Non-
601 * Periodic Transmit Request Queue. This queue holds both IN
602 * and OUT requests in Host mode. Device mode has only IN
604 * * 8'h0: Non-Periodic Transmit Request Queue is full
609 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
610 * Indicates the amount of free space available in the Non-
612 * Values are in terms of 32-bit words.
613 * * 16'h0: Non-Periodic TxFIFO is full
634 * The application uses this register to reset various hardware features inside
642 * Indicates that the AHB Master State Machine is in the IDLE
645 * Indicates that the DMA request is in progress. Used for debug.
650 * * 5'h0: Non-Periodic TxFIFO flush
651 * * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
652 * TxFIFO flush in Host mode
653 * * 5'h2: Periodic TxFIFO 2 flush in Device mode
654 * - ...
655 * * 5'hF: Periodic TxFIFO 15 flush in Device mode
656 * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
660 * cannot do so if the core is in the midst of a transaction.
661 * The application must only write this bit after checking that the
664 * The application must wait until the core clears this bit before
668 * The application can flush the entire RxFIFO using this bit, but
669 * must first ensure that the core is not in the middle of a
671 * The application must only write to this bit after checking that
674 * The application must wait until the bit is cleared before
677 * @intknqflsh: IN Token Sequence Learning Queue Flush (INTknQFlsh)
678 * The application writes this bit to flush the IN Token Sequence
681 * The application writes this bit to reset the (micro)frame number
686 * The application uses this bit to flush the control logic in the
689 * * All state machines in the AHB clock domain are reset to the
697 * * Because interrupt status bits are not cleared, the application
700 * This is a self-clearing bit that the core clears after all
701 * necessary logic is reset in the core. This may take several
707 * - PCGCCTL.RstPdwnModule
708 * - PCGCCTL.GateHclk
709 * - PCGCCTL.PwrClmp
710 * - PCGCCTL.StopPPhyLPwrClkSelclk
711 * - GUSBCFG.PhyLPwrClkSel
712 * - GUSBCFG.DDRSel
713 * - GUSBCFG.PHYSel
714 * - GUSBCFG.FSIntf
715 * - GUSBCFG.ULPI_UTMI_Sel
716 * - GUSBCFG.PHYIf
717 * - HCFG.FSLSPclkSel
718 * - DCFG.DevSpd
726 * The application can write to this bit any time it wants to reset
727 * the core. This is a self-clearing bit and the core clears this
728 * bit after all the necessary logic is reset in the core, which
737 * in the USB configuration registers listed above. When you
739 * selected and used in the PHY domain. Once a new clock is
762 * The application can program the RAM size that must be allocated to the
770 * This value is in terms of 32-bit words.
788 * This Description is only valid when the core is in Host Mode. For Device Mode
791 * same offset in the O2P USB core. The offset difference shown in this
801 * * 4'b0010: IN data packet received
802 * * 4'b0011: IN transfer completed (triggers an interrupt)
812 * Indicates the byte count of the received IN data packet
832 * This register can be used to configure the core after power-on or a changing
833 * to Host mode or Device mode. It contains USB and USB-PHY related
834 * configuration parameters. The application must program this register before
844 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel)
846 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
847 * FS and LS modes, the PHY can usually operate on a 48-MHz
849 * * 1'b0: 480-MHz Internal PLL clock
850 * * 1'b1: 48-MHz External Clock
851 * In 480 MHz mode, the UTMI interface operates at either 60 or
852 * 30-MHz, depending upon whether 8- or 16-bit data width is
853 * selected. In 48-MHz mode, the UTMI interface operates at 48
854 * MHz in FS mode and at either 48 or 6 MHz in LS mode
859 * Sets the turnaround time in PHY clocks.
863 * @hnpcap: HNP-Capable (HNPCap)
865 * @srpcap: SRP-Capable (SRPCap)
869 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
871 * @fsintf: Full-Speed Serial Interface Select (FSIntf)
878 * The number of PHY clocks that the application programs in this
879 * field is added to the high-speed/full-speed interpacket timeout
880 * duration in the core to account for any additional delays
882 * introduced by the PHY in generating the linestate condition may
884 * The USB standard timeout value for high-speed operation is
886 * value for full-speed operation is 16 to 18 (inclusive) bit
887 * times. The application must program this field based on the
890 * High-speed operation:
891 * * One 30-MHz PHY clock = 16 bit times
892 * * One 60-MHz PHY clock = 8 bit times
893 * Full-speed operation:
894 * * One 30-MHz PHY clock = 0.4 bit times
895 * * One 60-MHz PHY clock = 0.2 bit times
896 * * One 48-MHz PHY clock = 0.25 bit times
922 * register interrupts the application using the Host Channels Interrupt bit of
923 * the Core Interrupt register (GINTSTS.HChInt). This is shown in Interrupt.
924 * There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in
925 * this register are set and cleared when the application sets and clears bits
926 * in the corresponding Host Channel-n Interrupt register.
948 * Interrupt register to interrupt the application when an event occurs on a
970 * Host Channel-n Characteristics Register (HCCHAR)
978 * This field is set by the application and cleared by the OTG
983 * The application sets this bit to stop transmitting/receiving
985 * complete. The application must wait for the Channel Disabled
988 * This field is set (reset) by the application to indicate that
989 * the OTG host must perform a transfer in an odd (micro)frame.
998 * When the Split Enable bit of the Host Channel-n Split Control
1018 * @lspddev: Low-Speed Device (LSpdDev)
1019 * This field is set by the application to indicate that this
1020 * channel is communicating to a low-speed device.
1022 * Indicates whether the transaction is IN or OUT.
1024 * * 1'b1: IN
1052 * This register configures the core after power-on. Do not make changes to this
1059 * @fslssupp: FS- and LS-Only Support (FSLSSupp)
1060 * The application uses this bit to control the core's enumeration
1061 * speed. Using this bit, the application can make the core
1067 * * 1'b1: FS/LS-only, even if the connected device can support HS
1069 * When the core is in FS Host mode
1073 * When the core is in LS Host mode
1080 * * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
1098 * Host Channel-n Interrupt Register (HCINT)
1100 * This register indicates the status of a channel with respect to USB- and
1101 * AHB-related events. The application must read this register when the Host
1103 * set. Before the application can read this register, it must first read
1105 * number for the Host Channel-n Interrupt register. The application must clear
1106 * the appropriate bit in this register to clear the corresponding bits in the
1124 * any USB transaction error or in response to disable request by
1125 * the application.
1149 * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1151 * This register reflects the mask for each channel status described in the
1191 * Host Channel-n Split Control Register (HCSPLT)
1199 * The application sets this field to indicate that this channel is
1202 * The application sets this field to request the OTG host to
1236 * Host Channel-n Transfer Size Register (HCTSIZ)
1246 * The application programs this field with the type of PID to use
1252 * * 2'b11: MDATA (non-control)/SETUP (control)
1254 * This field is programmed by the application with the expected
1255 * number of packets to be transmitted (OUT) or received (IN).
1257 * transmission or reception of an OUT/IN packet. Once this count
1258 * reaches zero, the application is interrupted to indicate normal
1263 * For an IN, this field is the buffer size that the application
1264 * has reserved for the transfer. The application is expected to
1266 * size for IN transactions (periodic and non-periodic).
1290 * The value that the application programs to this field specifies
1291 * the interval between two consecutive SOFs (FS) or micro-
1292 * SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1294 * interval. The default value set in this field for a FS operation
1295 * when the PHY clock frequency is 60 MHz. The application can
1299 * the value based on the PHY clock specified in the FS/LS PHY
1319 * It also indicates the time remaining (in terms of the number of PHY clocks)
1320 * in the current (micro)frame.
1327 * Indicates the amount of time remaining in the current
1328 * microframe (HS) or frame (FS/LS), in terms of PHY clocks.
1330 * zero, this field is reloaded with the value in the Frame
1348 * This register is available in both Host and Device modes.
1350 * A single register holds USB port-related information such as USB reset,
1352 * R_SS_WC bits in this register can trigger an interrupt to the application
1354 * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this
1356 * the application must write a 1 to the bit to clear the interrupt.
1369 * The application writes a nonzero value to this field to put
1379 * PrtSpd must be zero (i.e. the interface must be in high-speed
1382 * The application uses this field to control power to this port,
1388 * * Bit [10]: Logic level of D-
1391 * When the application sets this bit, a reset sequence is
1392 * started on this port. The application must time the reset
1395 * * 1'b0: Port not in reset
1396 * * 1'b1: Port in reset
1397 * The application must leave this bit set for at least a
1399 * port. The application can leave it set for another 10 ms in
1406 * The application sets this bit to put this port in Suspend
1408 * To stop the PHY clock, the application must set the Port
1413 * remote wakeup signal is detected or the application sets
1414 * the Port Reset bit or Port Resume bit in this register or the
1416 * Disconnect Detected Interrupt bit in the Core Interrupt
1419 * * 1'b0: Port not in Suspend mode
1420 * * 1'b1: Port in Suspend mode
1422 * The application sets this bit to drive resume signaling on
1424 * until the application clears this bit.
1429 * signaling without application intervention and clears this bit
1437 * Overcurrent Active bit (bit 4) in this register changes.
1448 * condition, or by the application clearing this bit. The
1449 * application cannot set this bit by a register write. It can only
1451 * interrupt to the application.
1456 * to trigger an interrupt to the application using the Host Port
1458 * The application must write a 1 to this bit to clear the
1490 * TxFIFO, as shown in Figures 310 and 311.
1497 * This value is in terms of 32-bit words.
1514 * This read-only register contains the free space information for the Periodic
1522 * This indicates the entry in the Periodic Tx Request Queue that
1526 * - 1'b0: send in even (micro)frame
1527 * - 1'b1: send in odd (micro)frame
1530 * - 2'b00: IN/OUT
1531 * - 2'b01: Zero-length packet
1532 * - 2'b10: CSPLIT
1533 * - 2'b11: Disable channel command
1539 * in the Periodic Transmit Request Queue. This queue holds both
1540 * IN and OUT requests.
1549 * to in the Periodic TxFIFO.
1550 * Values are in terms of 32-bit words
1585 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
1586 * generate the hclk in the USB Subsystem is held
1587 * in reset. This bit must be set to '0' before
1588 * changing the value os DIVIDE in this register.
1591 * @p_x_on: Force USB-PHY on during suspend.
1592 * '1' USB-PHY XO block is powered-down during
1594 * '0' USB-PHY XO block is powered-up during
1600 * '0' The USB-PHY uses a 12MHz crystal as a clock source
1604 * USB_XO pin. USB_XI should be tied to ground in this
1615 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
1616 * remain powered in Suspend Mode.
1617 * '1' The USB-PHY XO Bias, Bandgap and PLL are
1618 * powered down in suspend mode.
1633 * in the USBC, for normal operation this must be '0'.
1642 * the phy_clk functionality in the USB Subsystem is
1643 * help in reset. This bit should not be set to '1'
1649 * the hclk functioanlity in the USB Subsystem is
1650 * held in reset.This bit should not be set to '1'
1698 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
1705 * @lsbist: Low-Speed BIST Enable.
1706 * @fsbist: Full-Speed BIST Enable.
1707 * @hsbist: High-Speed BIST Enable.
1717 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
1721 * - still provide 3.3V to USB_VDD33, and
1722 * - tie USB_REXT to 3.3V supply, and
1723 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
1724 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
1726 * with byte-counts between packets. When set to 0
1728 * 4-byte aligned address after adding byte-count.
1733 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
1734 * This signal enables the pull-down resistance on
1735 * the D+ line. '1' pull down-resistance is connected
1738 * (downstream-facing port), dp_pulldown and
1741 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
1742 * This signal enables the pull-down resistance on
1743 * the D- line. '1' pull down-resistance is connected
1744 * to D-. '0' pull down resistance is not connected
1745 * to D-. When an A/B device is acting as a host
1746 * (downstream-facing port), dp_pulldown and
1751 * set while the USB is in reset.
1752 * @tuning: Transmitter Tuning for High-Speed Operation.
1754 * times for high-speed operation.
1769 * when bit-stuffing is enabled.
1772 * when bit-stuffing is enabled.
1783 * @bist_enb: Built-In Self Test Enable.
1784 * Used to activate BIST in the PHY.
1798 * powered up (not in Susned Mode), an automatic
1800 * free_clk, then re-enable them with an aligned
1805 * de-assertion.