Lines Matching full:application
110 * The application must program this register as part of the O2P USB core
142 * The application uses this bit to mask or unmask the interrupt
145 * * 1'b0: Mask the interrupt assertion to the application.
146 * * 1'b1: Unmask the interrupt assertion to the application.
195 * The application uses this bit to indicate the O2P USB core's
236 * application. When an interrupt bit is masked, the interrupt associated with
324 * This register interrupts the application for system-level events in the
329 * type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status
368 * application must read the Host All Channels Interrupt (HAINT)
372 * cause of the interrupt. The application must clear the
376 * one of the O2P USB core ports in Host mode. The application must
379 * application must clear the appropriate status bit in the Host
385 * Queue space. This interrupt is used by the application for an
406 * application must read the Device All Endpoints Interrupt
411 * application must clear the appropriate status bit in the
416 * application must read the Device All Endpoints Interrupt
421 * application must clear the appropriate status bit in the
427 * mismatch count programmed by the application has expired.
439 * complete. The application must read the Device Status (DSTS)
458 * register (DCTL.SGOUTNak), set by the application, has taken
465 * application, has taken effect in the core. That is, the core has
466 * sampled the Global IN NAK bit set by the application. This bit
485 * USB. The application must write a 1 to this bit to clear the
488 * SOF token has been received on the USB. The application can read
494 * application must read the OTG Interrupt Status (GOTGINT)
496 * interrupt. The application must clear the appropriate status bit
499 * The core sets this bit when the application is trying to access:
554 * The application can program the RAM size and the memory start address for the
634 * The application uses this register to reset various hardware features inside
661 * The application must only write this bit after checking that the
664 * The application must wait until the core clears this bit before
668 * The application can flush the entire RxFIFO using this bit, but
671 * The application must only write to this bit after checking that
674 * The application must wait until the bit is cleared before
678 * The application writes this bit to flush the IN Token Sequence
681 * The application writes this bit to reset the (micro)frame number
686 * The application uses this bit to flush the control logic in the
697 * * Because interrupt status bits are not cleared, the application
726 * The application can write to this bit any time it wants to reset
762 * The application can program the RAM size that must be allocated to the
834 * configuration parameters. The application must program this register before
878 * The number of PHY clocks that the application programs in this
887 * times. The application must program this field based on the
922 * register interrupts the application using the Host Channels Interrupt bit of
925 * this register are set and cleared when the application sets and clears bits
948 * Interrupt register to interrupt the application when an event occurs on a
978 * This field is set by the application and cleared by the OTG
983 * The application sets this bit to stop transmitting/receiving
985 * complete. The application must wait for the Channel Disabled
988 * This field is set (reset) by the application to indicate that
1019 * This field is set by the application to indicate that this
1060 * The application uses this bit to control the core's enumeration
1061 * speed. Using this bit, the application can make the core
1101 * AHB-related events. The application must read this register when the Host
1103 * set. Before the application can read this register, it must first read
1105 * number for the Host Channel-n Interrupt register. The application must clear
1125 * the application.
1199 * The application sets this field to indicate that this channel is
1202 * The application sets this field to request the OTG host to
1246 * The application programs this field with the type of PID to use
1254 * This field is programmed by the application with the expected
1258 * reaches zero, the application is interrupted to indicate normal
1263 * For an IN, this field is the buffer size that the application
1264 * has reserved for the transfer. The application is expected to
1290 * The value that the application programs to this field specifies
1295 * when the PHY clock frequency is 60 MHz. The application can
1352 * R_SS_WC bits in this register can trigger an interrupt to the application
1354 * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this
1356 * the application must write a 1 to the bit to clear the interrupt.
1369 * The application writes a nonzero value to this field to put
1382 * The application uses this field to control power to this port,
1391 * When the application sets this bit, a reset sequence is
1392 * started on this port. The application must time the reset
1397 * The application must leave this bit set for at least a
1399 * port. The application can leave it set for another 10 ms in
1406 * The application sets this bit to put this port in Suspend
1408 * To stop the PHY clock, the application must set the Port
1413 * remote wakeup signal is detected or the application sets
1422 * The application sets this bit to drive resume signaling on
1424 * until the application clears this bit.
1429 * signaling without application intervention and clears this bit
1448 * condition, or by the application clearing this bit. The
1449 * application cannot set this bit by a register write. It can only
1451 * interrupt to the application.
1456 * to trigger an interrupt to the application using the Host Port
1458 * The application must write a 1 to this bit to clear the