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1 /* SPDX-License-Identifier: GPL-2.0 */
3 * omap_udc.h -- for omap 3.2 udc, with OTG support
15 # define UDC_SETUP_SEL (1 << 6)
16 # define UDC_EP_SEL (1 << 5)
17 # define UDC_EP_DIR (1 << 4)
21 # define UDC_CLR_HALT (1 << 7)
22 # define UDC_SET_HALT (1 << 6)
23 # define UDC_CLRDATA_TOGGLE (1 << 3)
24 # define UDC_SET_FIFO_EN (1 << 2)
25 # define UDC_CLR_EP (1 << 1)
26 # define UDC_RESET_EP (1 << 0)
28 # define UDC_NO_RXPACKET (1 << 15)
29 # define UDC_MISS_IN (1 << 14)
30 # define UDC_DATA_FLUSH (1 << 13)
31 # define UDC_ISO_ERR (1 << 12)
32 # define UDC_ISO_FIFO_EMPTY (1 << 9)
33 # define UDC_ISO_FIFO_FULL (1 << 8)
34 # define UDC_EP_HALTED (1 << 6)
35 # define UDC_STALL (1 << 5)
36 # define UDC_NAK (1 << 4)
37 # define UDC_ACK (1 << 3)
38 # define UDC_FIFO_EN (1 << 2)
39 # define UDC_NON_ISO_FIFO_EMPTY (1 << 1)
40 # define UDC_NON_ISO_FIFO_FULL (1 << 0)
42 #define UDC_SYSCON1 (UDC_BASE + 0x18) /* System config 1 */
43 # define UDC_CFG_LOCK (1 << 8)
44 # define UDC_DATA_ENDIAN (1 << 7)
45 # define UDC_DMA_ENDIAN (1 << 6)
46 # define UDC_NAK_EN (1 << 4)
47 # define UDC_AUTODECODE_DIS (1 << 3)
48 # define UDC_SELF_PWR (1 << 2)
49 # define UDC_SOFF_DIS (1 << 1)
50 # define UDC_PULLUP_EN (1 << 0)
52 # define UDC_RMT_WKP (1 << 6)
53 # define UDC_STALL_CMD (1 << 5)
54 # define UDC_DEV_CFG (1 << 3)
55 # define UDC_CLR_CFG (1 << 2)
57 # define UDC_B_HNP_ENABLE (1 << 9)
58 # define UDC_A_HNP_SUPPORT (1 << 8)
59 # define UDC_A_ALT_HNP_SUPPORT (1 << 7)
60 # define UDC_R_WK_OK (1 << 6)
61 # define UDC_USB_RESET (1 << 5)
62 # define UDC_SUS (1 << 4)
63 # define UDC_CFG (1 << 3)
64 # define UDC_ADD (1 << 2)
65 # define UDC_DEF (1 << 1)
66 # define UDC_ATT (1 << 0)
68 # define UDC_FT_LOCK (1 << 12)
69 # define UDC_TS_OK (1 << 11)
72 # define UDC_SOF_IE (1 << 7)
73 # define UDC_EPN_RX_IE (1 << 5)
74 # define UDC_EPN_TX_IE (1 << 4)
75 # define UDC_DS_CHG_IE (1 << 3)
76 # define UDC_EP0_IE (1 << 0)
78 /* rx/tx dma channels numbered 1-3 not 0-2 */
79 # define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2))
80 # define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3))
81 # define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4))
83 # define UDC_TXN_DONE (1 << 10)
84 # define UDC_RXN_CNT (1 << 9)
85 # define UDC_RXN_EOT (1 << 8)
86 # define UDC_IRQ_SOF (1 << 7)
87 # define UDC_EPN_RX (1 << 5)
88 # define UDC_EPN_TX (1 << 4)
89 # define UDC_DS_CHG (1 << 3)
90 # define UDC_SETUP (1 << 2)
91 # define UDC_EP0_RX (1 << 1)
92 # define UDC_EP0_TX (1 << 0)
96 # define UDC_DMA_RX_SB (1 << 12)
103 # define UDC_DMA_REQ (1 << 12)
107 /* rx/tx dma control, numbering channels 1-3 not 0-2 */
108 #define UDC_TXDMA(chan) (UDC_BASE + 0x50 - 4 + 4 * (chan))
109 # define UDC_TXN_EOT (1 << 15) /* bytes vs packets */
110 # define UDC_TXN_START (1 << 14) /* start transfer */
112 #define UDC_RXDMA(chan) (UDC_BASE + 0x60 - 4 + 4 * (chan))
113 # define UDC_RXN_STOP (1 << 15) /* enable EOT irq */
122 # define UDC_EPN_RX_VALID (1 << 15)
123 # define UDC_EPN_RX_DB (1 << 14)
125 # define UDC_EPN_RX_ISO (1 << 11)
130 /*-------------------------------------------------------------------------*/
136 unsigned mapped:1;
148 unsigned double_buf:1;
149 unsigned stopped:1;
150 unsigned fnf:1;
151 unsigned has_dma:1;
169 unsigned softconnect:1;
170 unsigned vbus_active:1;
171 unsigned ep0_pending:1;
172 unsigned ep0_in:1;
173 unsigned ep0_set_config:1;
174 unsigned ep0_reset_config:1;
175 unsigned ep0_setup:1;
179 unsigned clk_requested:1;
182 /*-------------------------------------------------------------------------*/
195 /*-------------------------------------------------------------------------*/
198 #define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */
201 #define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */
202 #define VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */
204 #define HMC_1510 ((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f)